PPC: Get MMU state on register sync

Submitted by Alexander Graf on Dec. 2, 2009, 10:19 p.m.

Details

Message ID 1259792387-24237-1-git-send-email-agraf@suse.de
State New
Headers show

Commit Message

Alexander Graf Dec. 2, 2009, 10:19 p.m.
While x86 only needs to sync cr0-4 to know all about its MMU state and enable
qemu to resolve virtual to physical addresses, we need to sync all of the
segment registers on PPC to know which mapping we're in.

So let's grab the segment register contents to be able to use the "x" monitor
command and also enable the gdbstub to resolve virtual addresses.

I sent the corresponding KVM patch to the KVM ML some minutes ago.

Signed-off-by: Alexander Graf <agraf@suse.de>

---

v1 -> v2:

  - adjust to kernel header changes
---
 target-ppc/kvm.c |   30 ++++++++++++++++++++++++++++++
 1 files changed, 30 insertions(+), 0 deletions(-)

Patch hide | download patch | download mbox

diff --git a/target-ppc/kvm.c b/target-ppc/kvm.c
index 4e1c65f..74421b5 100644
--- a/target-ppc/kvm.c
+++ b/target-ppc/kvm.c
@@ -98,12 +98,17 @@  int kvm_arch_put_registers(CPUState *env)
 int kvm_arch_get_registers(CPUState *env)
 {
     struct kvm_regs regs;
+    struct kvm_sregs sregs;
     uint32_t i, ret;
 
     ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
     if (ret < 0)
         return ret;
 
+    ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
+    if (ret < 0)
+        return ret;
+
     env->ctr = regs.ctr;
     env->lr = regs.lr;
     env->xer = regs.xer;
@@ -125,6 +130,31 @@  int kvm_arch_get_registers(CPUState *env)
     for (i = 0;i < 32; i++)
         env->gpr[i] = regs.gpr[i];
 
+#ifdef KVM_CAP_PPC_SEGSTATE
+    if (kvm_check_extension(env->kvm_state, KVM_CAP_PPC_SEGSTATE)) {
+        env->sdr1 = sregs.u.s.sdr1;
+    
+        /* Sync SLB */
+        for (i = 0; i < 64; i++) {
+            ppc_store_slb(env, sregs.u.s.ppc64.slb[i].slbe,
+                               sregs.u.s.ppc64.slb[i].slbv);
+        }
+    
+        /* Sync SRs */
+        for (i = 0; i < 16; i++) {
+            env->sr[i] = sregs.u.s.ppc32.sr[i];
+        }
+    
+        /* Sync BATs */
+        for (i = 0; i < 8; i++) {
+            env->DBAT[0][i] = sregs.u.s.ppc32.dbat[i] & 0xffffffff;
+            env->DBAT[1][i] = sregs.u.s.ppc32.dbat[i] >> 32;
+            env->IBAT[0][i] = sregs.u.s.ppc32.ibat[i] & 0xffffffff;
+            env->IBAT[1][i] = sregs.u.s.ppc32.ibat[i] >> 32;
+        }
+    }
+#endif
+
     return 0;
 }