| Message ID | 1413744219-6859-6-git-send-email-marex@denx.de |
|---|---|
| State | Superseded |
| Delegated to: | Jagannadha Sutradharudu Teki |
| Headers | show |
On 20 October 2014 00:13, Marek Vasut <marex@denx.de> wrote: > Add short documentation-alike note on how to use the Altera SPI > driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V. > > Signed-off-by: Marek Vasut <marex@denx.de> > Cc: Chin Liang See <clsee@altera.com> > Cc: Dinh Nguyen <dinguyen@altera.com> > Cc: Albert Aribaud <albert.u.boot@aribaud.net> > Cc: Tom Rini <trini@ti.com> > Cc: Wolfgang Denk <wd@denx.de> > Cc: Pavel Machek <pavel@denx.de> > Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> > --- > drivers/spi/altera_spi.c | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c > index 3065e96..0566e4f 100644 > --- a/drivers/spi/altera_spi.c > +++ b/drivers/spi/altera_spi.c > @@ -4,6 +4,14 @@ > * based on bfin_spi.c > * Copyright (c) 2005-2008 Analog Devices Inc. > * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> > + * Copyright (C) 2014 Marek Vasut <marex@denx.de> Looks not good to me - with few changes. > + * > + * SoCFPGA EPCS/EPCQx1 mini howto: > + * - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild > + * - The controller base address is the "Base" in QSys + 0x400 > + * - Set MSEL[4:0]=10010 (AS Standard) > + * - Load the bitstream into FPGA, enable bridges > + * - Only then will the driver work Instead of here, Pls- try to test any hardware with this written sequence with the obtained logs copy that info on doc/SPI we're maintaining the test in this format. Testing the written sequence with logs are more authentic than listing on a driver file. > * > * SPDX-License-Identifier: GPL-2.0+ > */ > -- > 2.1.1 > thanks!
On Monday, October 20, 2014 at 05:10:17 PM, Jagan Teki wrote: [...] > > * based on bfin_spi.c > > * Copyright (c) 2005-2008 Analog Devices Inc. > > * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> > > > > + * Copyright (C) 2014 Marek Vasut <marex@denx.de> > > Looks not good to me - with few changes. > > > + * > > + * SoCFPGA EPCS/EPCQx1 mini howto: > > + * - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild > > + * - The controller base address is the "Base" in QSys + 0x400 > > + * - Set MSEL[4:0]=10010 (AS Standard) > > + * - Load the bitstream into FPGA, enable bridges > > + * - Only then will the driver work > > Instead of here, > Pls- try to test any hardware with this written sequence with the > obtained logs copy > that info on doc/SPI we're maintaining the test in this format. > > Testing the written sequence with logs are more authentic than listing > on a driver file. Excuse me, but I don't quite understand what you're asking of me, sorry. Best regards, Marek Vasut
On 20 October 2014 20:43, Marek Vasut <marex@denx.de> wrote: > On Monday, October 20, 2014 at 05:10:17 PM, Jagan Teki wrote: > > [...] > >> > * based on bfin_spi.c >> > * Copyright (c) 2005-2008 Analog Devices Inc. >> > * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> >> > >> > + * Copyright (C) 2014 Marek Vasut <marex@denx.de> >> >> Looks not good to me - with few changes. >> >> > + * >> > + * SoCFPGA EPCS/EPCQx1 mini howto: >> > + * - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild >> > + * - The controller base address is the "Base" in QSys + 0x400 >> > + * - Set MSEL[4:0]=10010 (AS Standard) >> > + * - Load the bitstream into FPGA, enable bridges >> > + * - Only then will the driver work >> >> Instead of here, >> Pls- try to test any hardware with this written sequence with the >> obtained logs copy >> that info on doc/SPI we're maintaining the test in this format. >> >> Testing the written sequence with logs are more authentic than listing >> on a driver file. > > Excuse me, but I don't quite understand what you're asking of me, sorry. OK, the steps you written is looks like a usage of driver on specific module, my point here was instead of placing these into driver file try to verify the same steps on hardware with the help of simple spi tests and place the same file on doc/SPI/ . It's a well showed prof that this driver is working with this kind of steps. thanks!
diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 3065e96..0566e4f 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -4,6 +4,14 @@ * based on bfin_spi.c * Copyright (c) 2005-2008 Analog Devices Inc. * Copyright (C) 2010 Thomas Chou <thomas@wytron.com.tw> + * Copyright (C) 2014 Marek Vasut <marex@denx.de> + * + * SoCFPGA EPCS/EPCQx1 mini howto: + * - Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild + * - The controller base address is the "Base" in QSys + 0x400 + * - Set MSEL[4:0]=10010 (AS Standard) + * - Load the bitstream into FPGA, enable bridges + * - Only then will the driver work * * SPDX-License-Identifier: GPL-2.0+ */
Add short documentation-alike note on how to use the Altera SPI driver with the EPCS/EPCQx1 FPGA IP block on SoCFPGA Cyclone V. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Albert Aribaud <albert.u.boot@aribaud.net> Cc: Tom Rini <trini@ti.com> Cc: Wolfgang Denk <wd@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> --- drivers/spi/altera_spi.c | 8 ++++++++ 1 file changed, 8 insertions(+)