| Message ID | 1413445963-24706-2-git-send-email-richard.zhu@freescale.com |
|---|---|
| State | Superseded |
| Headers | show |
Am Donnerstag, den 16.10.2014, 15:52 +0800 schrieb Richard Zhu: > From: Richard Zhu <r65037@freescale.com> > > - move "program correct class for RC" from dw_pcie_host_init() > to dw_pcie_setup_rc(). since this is RC setup, it's > better to contained in dw_pcie_setup_rc function. > Then, RC can be re-setup really by dw_pcie_setup_rc(). > - add one store/re-store msi cfg functions. Because that > pcie controller maybe powered off during system suspend, > and the msi data configuration would be lost. > these functions can be used to store/restore the msi data > and msi_enable during the suspend/resume callback. > > Signed-off-by: Richard Zhu <richard.zhu@freescale.com> NAK for the reasons below. > --- > drivers/pci/host/pcie-designware.c | 21 ++++++++++++++++++--- > drivers/pci/host/pcie-designware.h | 3 +++ > 2 files changed, 21 insertions(+), 3 deletions(-) > > diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c > index 538bbf3..b1f82ff 100644 > --- a/drivers/pci/host/pcie-designware.c > +++ b/drivers/pci/host/pcie-designware.c > @@ -194,6 +194,19 @@ void dw_pcie_msi_init(struct pcie_port *pp) > dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); > } > > +void dw_pcie_msi_cfg_store(struct pcie_port *pp) > +{ > + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_enable); You are only saving and restoring this one register. While this might work for the current implementation that uses only a max of 32 vectors this is not true in general. At least the imx6 implementation supports up to 128 vectors, so actually 4 registers might be used here. > +} > + > +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) > +{ > + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, > + virt_to_phys((void *)pp->msi_data)); > + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); > + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_enable); Murali asked you to take into account the newly added requirements for older designware cores. You did not. > +} > + > static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) > { > int flag = 1; > @@ -570,9 +583,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) > > dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); > > - /* program correct class for RC */ > - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); > - > dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); > val |= PORT_LOGIC_SPEED_CHANGE; > dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); > @@ -917,6 +927,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) > val = memlimit | membase; > dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); > > + /* program correct class for RC */ > + dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val); > + val |= PCI_CLASS_BRIDGE_PCI << 16; > + dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION); > + This is getting ridiculous. How many time did I ask you to change this now. This hunk should just read: + /* program correct class for RC */ + dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); + > /* setup command register */ > dw_pcie_readl_rc(pp, PCI_COMMAND, &val); > val &= 0xffff0000; > diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h > index a476e60..b0bfed0 100644 > --- a/drivers/pci/host/pcie-designware.h > +++ b/drivers/pci/host/pcie-designware.h > @@ -56,6 +56,7 @@ struct pcie_port { > int msi_irq; > struct irq_domain *irq_domain; > unsigned long msi_data; > + unsigned int msi_enable; > DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); > }; > > @@ -83,6 +84,8 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); > int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); > irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); > void dw_pcie_msi_init(struct pcie_port *pp); > +void dw_pcie_msi_cfg_store(struct pcie_port *pp); > +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); > int dw_pcie_link_up(struct pcie_port *pp); > void dw_pcie_setup_rc(struct pcie_port *pp); > int dw_pcie_host_init(struct pcie_port *pp); -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
DQo+IC0tLS0tT3JpZ2luYWwgTWVzc2FnZS0tLS0tDQo+IEZyb206IEx1Y2FzIFN0YWNoIFttYWls dG86bC5zdGFjaEBwZW5ndXRyb25peC5kZV0NCj4gU2VudDogVGh1cnNkYXksIE9jdG9iZXIgMTYs IDIwMTQgNjozNyBQTQ0KPiBUbzogUmljaGFyZCBaaHUNCj4gQ2M6IGxpbnV4LXBjaUB2Z2VyLmtl cm5lbC5vcmc7IEd1byBTaGF3bi1SNjUwNzM7IGZlc3RldmFtQGdtYWlsLmNvbTsNCj4gdGhhcnZl eUBnYXRld29ya3MuY29tOyBaaHUgUmljaGFyZC1SNjUwMzcNCj4gU3ViamVjdDogUmU6IFtQQVRD SCB2NiAwMS8xM10gUENJOiBkZXNpZ253YXJlOiBSZWZpbmUgc2V0dXBfcmMgYW5kIGFkZCBtc2kN Cj4gZGF0YSByZXN0b3JlDQo+IA0KPiBBbSBEb25uZXJzdGFnLCBkZW4gMTYuMTAuMjAxNCwgMTU6 NTIgKzA4MDAgc2NocmllYiBSaWNoYXJkIFpodToNCj4gPiBGcm9tOiBSaWNoYXJkIFpodSA8cjY1 MDM3QGZyZWVzY2FsZS5jb20+DQo+ID4NCj4gPiAtIG1vdmUgInByb2dyYW0gY29ycmVjdCBjbGFz cyBmb3IgUkMiIGZyb20gZHdfcGNpZV9ob3N0X2luaXQoKSB0bw0KPiA+IGR3X3BjaWVfc2V0dXBf cmMoKS4gc2luY2UgdGhpcyBpcyBSQyBzZXR1cCwgaXQncyBiZXR0ZXIgdG8gY29udGFpbmVkDQo+ ID4gaW4gZHdfcGNpZV9zZXR1cF9yYyBmdW5jdGlvbi4NCj4gPiBUaGVuLCBSQyBjYW4gYmUgcmUt c2V0dXAgcmVhbGx5IGJ5IGR3X3BjaWVfc2V0dXBfcmMoKS4NCj4gPiAtIGFkZCBvbmUgc3RvcmUv cmUtc3RvcmUgbXNpIGNmZyBmdW5jdGlvbnMuIEJlY2F1c2UgdGhhdCBwY2llDQo+ID4gY29udHJv bGxlciBtYXliZSBwb3dlcmVkIG9mZiBkdXJpbmcgc3lzdGVtIHN1c3BlbmQsIGFuZCB0aGUgbXNp IGRhdGENCj4gPiBjb25maWd1cmF0aW9uIHdvdWxkIGJlIGxvc3QuDQo+ID4gdGhlc2UgZnVuY3Rp b25zIGNhbiBiZSB1c2VkIHRvIHN0b3JlL3Jlc3RvcmUgdGhlIG1zaSBkYXRhIGFuZA0KPiA+IG1z aV9lbmFibGUgZHVyaW5nIHRoZSBzdXNwZW5kL3Jlc3VtZSBjYWxsYmFjay4NCj4gPg0KPiA+IFNp Z25lZC1vZmYtYnk6IFJpY2hhcmQgWmh1IDxyaWNoYXJkLnpodUBmcmVlc2NhbGUuY29tPg0KPiAN Cj4gTkFLIGZvciB0aGUgcmVhc29ucyBiZWxvdy4NCj4gDQo+ID4gLS0tDQo+ID4gIGRyaXZlcnMv cGNpL2hvc3QvcGNpZS1kZXNpZ253YXJlLmMgfCAyMSArKysrKysrKysrKysrKysrKystLS0NCj4g PiBkcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5oIHwgIDMgKysrDQo+ID4gIDIgZmls ZXMgY2hhbmdlZCwgMjEgaW5zZXJ0aW9ucygrKSwgMyBkZWxldGlvbnMoLSkNCj4gPg0KPiA+IGRp ZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+ID4gYi9kcml2 ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+ID4gaW5kZXggNTM4YmJmMy4uYjFmODJm ZiAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5jDQo+ ID4gKysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuYw0KPiA+IEBAIC0xOTQs NiArMTk0LDE5IEBAIHZvaWQgZHdfcGNpZV9tc2lfaW5pdChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCkN Cj4gPiAgCWR3X3BjaWVfd3Jfb3duX2NvbmYocHAsIFBDSUVfTVNJX0FERFJfSEksIDQsIDApOyAg fQ0KPiA+DQo+ID4gK3ZvaWQgZHdfcGNpZV9tc2lfY2ZnX3N0b3JlKHN0cnVjdCBwY2llX3BvcnQg KnBwKSB7DQo+ID4gKwlkd19wY2llX3JkX293bl9jb25mKHBwLCBQQ0lFX01TSV9JTlRSMF9FTkFC TEUsIDQsICZwcC0+bXNpX2VuYWJsZSk7DQo+IA0KPiBZb3UgYXJlIG9ubHkgc2F2aW5nIGFuZCBy ZXN0b3JpbmcgdGhpcyBvbmUgcmVnaXN0ZXIuIFdoaWxlIHRoaXMgbWlnaHQgd29yayBmb3INCj4g dGhlIGN1cnJlbnQgaW1wbGVtZW50YXRpb24gdGhhdCB1c2VzIG9ubHkgYSBtYXggb2YgMzIgdmVj dG9ycyB0aGlzIGlzIG5vdCB0cnVlDQo+IGluIGdlbmVyYWwuIEF0IGxlYXN0IHRoZSBpbXg2IGlt cGxlbWVudGF0aW9uIHN1cHBvcnRzIHVwIHRvIDEyOCB2ZWN0b3JzLCBzbw0KPiBhY3R1YWxseSA0 IHJlZ2lzdGVycyBtaWdodCBiZSB1c2VkIGhlcmUuDQo+DQpbUmljaGFyZF0gT2ssIGFsbCB0aGUg Zm91ciByZWdpc3RlcnMgd291bGQgYmUgc3RvcmVkL3JlLXN0b3JlZC4NCiANCj4gPiArfQ0KPiA+ ICsNCj4gPiArdm9pZCBkd19wY2llX21zaV9jZmdfcmVzdG9yZShzdHJ1Y3QgcGNpZV9wb3J0ICpw cCkgew0KPiA+ICsJZHdfcGNpZV93cl9vd25fY29uZihwcCwgUENJRV9NU0lfQUREUl9MTywgNCwN Cj4gPiArCQkJdmlydF90b19waHlzKCh2b2lkICopcHAtPm1zaV9kYXRhKSk7DQo+ID4gKwlkd19w Y2llX3dyX293bl9jb25mKHBwLCBQQ0lFX01TSV9BRERSX0hJLCA0LCAwKTsNCj4gPiArCWR3X3Bj aWVfd3Jfb3duX2NvbmYocHAsIFBDSUVfTVNJX0lOVFIwX0VOQUJMRSwgNCwgcHAtPm1zaV9lbmFi bGUpOw0KPiANCj4gTXVyYWxpIGFza2VkIHlvdSB0byB0YWtlIGludG8gYWNjb3VudCB0aGUgbmV3 bHkgYWRkZWQgcmVxdWlyZW1lbnRzIGZvciBvbGRlcg0KPiBkZXNpZ253YXJlIGNvcmVzLiBZb3Ug ZGlkIG5vdC4NCltSaWNoYXJkXSBTb3JyeSwgTXVyYWxpJ3MgY29tbWVudHMgaXMgbWlzc2VkIGJl Zm9yZSwgd291bGQgYmUgYWRkZWQgbGF0ZXIuDQo+IA0KPiA+ICt9DQo+ID4gKw0KPiA+ICBzdGF0 aWMgaW50IGZpbmRfdmFsaWRfcG9zMChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCwgaW50IG1zZ3ZlYywg aW50IHBvcywNCj4gPiBpbnQgKnBvczApICB7DQo+ID4gIAlpbnQgZmxhZyA9IDE7DQo+ID4gQEAg LTU3MCw5ICs1ODMsNiBAQCBpbnQgX19pbml0IGR3X3BjaWVfaG9zdF9pbml0KHN0cnVjdCBwY2ll X3BvcnQgKnBwKQ0KPiA+DQo+ID4gIAlkd19wY2llX3dyX293bl9jb25mKHBwLCBQQ0lfQkFTRV9B RERSRVNTXzAsIDQsIDApOw0KPiA+DQo+ID4gLQkvKiBwcm9ncmFtIGNvcnJlY3QgY2xhc3MgZm9y IFJDICovDQo+ID4gLQlkd19wY2llX3dyX293bl9jb25mKHBwLCBQQ0lfQ0xBU1NfREVWSUNFLCAy LCBQQ0lfQ0xBU1NfQlJJREdFX1BDSSk7DQo+ID4gLQ0KPiA+ICAJZHdfcGNpZV9yZF9vd25fY29u ZihwcCwgUENJRV9MSU5LX1dJRFRIX1NQRUVEX0NPTlRST0wsIDQsICZ2YWwpOw0KPiA+ICAJdmFs IHw9IFBPUlRfTE9HSUNfU1BFRURfQ0hBTkdFOw0KPiA+ICAJZHdfcGNpZV93cl9vd25fY29uZihw cCwgUENJRV9MSU5LX1dJRFRIX1NQRUVEX0NPTlRST0wsIDQsIHZhbCk7IEBADQo+ID4gLTkxNyw2 ICs5MjcsMTEgQEAgdm9pZCBkd19wY2llX3NldHVwX3JjKHN0cnVjdCBwY2llX3BvcnQgKnBwKQ0K PiA+ICAJdmFsID0gbWVtbGltaXQgfCBtZW1iYXNlOw0KPiA+ICAJZHdfcGNpZV93cml0ZWxfcmMo cHAsIHZhbCwgUENJX01FTU9SWV9CQVNFKTsNCj4gPg0KPiA+ICsJLyogcHJvZ3JhbSBjb3JyZWN0 IGNsYXNzIGZvciBSQyAqLw0KPiA+ICsJZHdfcGNpZV9yZWFkbF9yYyhwcCwgUENJX0NMQVNTX1JF VklTSU9OLCAmdmFsKTsNCj4gPiArCXZhbCB8PSBQQ0lfQ0xBU1NfQlJJREdFX1BDSSA8PCAxNjsN Cj4gPiArCWR3X3BjaWVfd3JpdGVsX3JjKHBwLCB2YWwsIFBDSV9DTEFTU19SRVZJU0lPTik7DQo+ ID4gKw0KPiANCj4gVGhpcyBpcyBnZXR0aW5nIHJpZGljdWxvdXMuIEhvdyBtYW55IHRpbWUgZGlk IEkgYXNrIHlvdSB0byBjaGFuZ2UgdGhpcyBub3cuDQo+IFRoaXMgaHVuayBzaG91bGQganVzdCBy ZWFkOg0KPiANCj4gKwkvKiBwcm9ncmFtIGNvcnJlY3QgY2xhc3MgZm9yIFJDICovDQo+ICsJZHdf cGNpZV93cl9vd25fY29uZihwcCwgUENJX0NMQVNTX0RFVklDRSwgMiwgUENJX0NMQVNTX0JSSURH RV9QQ0kpOw0KPiArDQo+IA0KW1JpY2hhcmRdIE9rLCB3b3VsZCBiZSBrZXB0IHRoaXMgd2F5LiBU aGFua3MuDQoNCj4gPiAgCS8qIHNldHVwIGNvbW1hbmQgcmVnaXN0ZXIgKi8NCj4gPiAgCWR3X3Bj aWVfcmVhZGxfcmMocHAsIFBDSV9DT01NQU5ELCAmdmFsKTsNCj4gPiAgCXZhbCAmPSAweGZmZmYw MDAwOw0KPiA+IGRpZmYgLS1naXQgYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5o DQo+ID4gYi9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVzaWdud2FyZS5oDQo+ID4gaW5kZXggYTQ3 NmU2MC4uYjBiZmVkMCAxMDA2NDQNCj4gPiAtLS0gYS9kcml2ZXJzL3BjaS9ob3N0L3BjaWUtZGVz aWdud2FyZS5oDQo+ID4gKysrIGIvZHJpdmVycy9wY2kvaG9zdC9wY2llLWRlc2lnbndhcmUuaA0K PiA+IEBAIC01Niw2ICs1Niw3IEBAIHN0cnVjdCBwY2llX3BvcnQgew0KPiA+ICAJaW50CQkJbXNp X2lycTsNCj4gPiAgCXN0cnVjdCBpcnFfZG9tYWluCSppcnFfZG9tYWluOw0KPiA+ICAJdW5zaWdu ZWQgbG9uZwkJbXNpX2RhdGE7DQo+ID4gKwl1bnNpZ25lZCBpbnQJCW1zaV9lbmFibGU7DQo+ID4g IAlERUNMQVJFX0JJVE1BUChtc2lfaXJxX2luX3VzZSwgTUFYX01TSV9JUlFTKTsgIH07DQo+ID4N Cj4gPiBAQCAtODMsNiArODQsOCBAQCBpbnQgZHdfcGNpZV9jZmdfcmVhZCh2b2lkIF9faW9tZW0g KmFkZHIsIGludCB3aGVyZSwNCj4gPiBpbnQgc2l6ZSwgdTMyICp2YWwpOyAgaW50IGR3X3BjaWVf Y2ZnX3dyaXRlKHZvaWQgX19pb21lbSAqYWRkciwgaW50DQo+ID4gd2hlcmUsIGludCBzaXplLCB1 MzIgdmFsKTsgIGlycXJldHVybl90IGR3X2hhbmRsZV9tc2lfaXJxKHN0cnVjdA0KPiA+IHBjaWVf cG9ydCAqcHApOyAgdm9pZCBkd19wY2llX21zaV9pbml0KHN0cnVjdCBwY2llX3BvcnQgKnBwKTsN Cj4gPiArdm9pZCBkd19wY2llX21zaV9jZmdfc3RvcmUoc3RydWN0IHBjaWVfcG9ydCAqcHApOyB2 b2lkDQo+ID4gK2R3X3BjaWVfbXNpX2NmZ19yZXN0b3JlKHN0cnVjdCBwY2llX3BvcnQgKnBwKTsN Cj4gPiAgaW50IGR3X3BjaWVfbGlua191cChzdHJ1Y3QgcGNpZV9wb3J0ICpwcCk7ICB2b2lkDQo+ ID4gZHdfcGNpZV9zZXR1cF9yYyhzdHJ1Y3QgcGNpZV9wb3J0ICpwcCk7ICBpbnQgZHdfcGNpZV9o b3N0X2luaXQoc3RydWN0DQo+ID4gcGNpZV9wb3J0ICpwcCk7DQo+IA0KDQoNCkJlc3QgUmVnYXJk cw0KUmljaGFyZCBaaHUNCg0K -- To unsubscribe from this list: send the line "unsubscribe linux-pci" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/drivers/pci/host/pcie-designware.c b/drivers/pci/host/pcie-designware.c index 538bbf3..b1f82ff 100644 --- a/drivers/pci/host/pcie-designware.c +++ b/drivers/pci/host/pcie-designware.c @@ -194,6 +194,19 @@ void dw_pcie_msi_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); } +void dw_pcie_msi_cfg_store(struct pcie_port *pp) +{ + dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, &pp->msi_enable); +} + +void dw_pcie_msi_cfg_restore(struct pcie_port *pp) +{ + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4, + virt_to_phys((void *)pp->msi_data)); + dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0); + dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE, 4, pp->msi_enable); +} + static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0) { int flag = 1; @@ -570,9 +583,6 @@ int __init dw_pcie_host_init(struct pcie_port *pp) dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0); - /* program correct class for RC */ - dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI); - dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val); val |= PORT_LOGIC_SPEED_CHANGE; dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val); @@ -917,6 +927,11 @@ void dw_pcie_setup_rc(struct pcie_port *pp) val = memlimit | membase; dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE); + /* program correct class for RC */ + dw_pcie_readl_rc(pp, PCI_CLASS_REVISION, &val); + val |= PCI_CLASS_BRIDGE_PCI << 16; + dw_pcie_writel_rc(pp, val, PCI_CLASS_REVISION); + /* setup command register */ dw_pcie_readl_rc(pp, PCI_COMMAND, &val); val &= 0xffff0000; diff --git a/drivers/pci/host/pcie-designware.h b/drivers/pci/host/pcie-designware.h index a476e60..b0bfed0 100644 --- a/drivers/pci/host/pcie-designware.h +++ b/drivers/pci/host/pcie-designware.h @@ -56,6 +56,7 @@ struct pcie_port { int msi_irq; struct irq_domain *irq_domain; unsigned long msi_data; + unsigned int msi_enable; DECLARE_BITMAP(msi_irq_in_use, MAX_MSI_IRQS); }; @@ -83,6 +84,8 @@ int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val); int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val); irqreturn_t dw_handle_msi_irq(struct pcie_port *pp); void dw_pcie_msi_init(struct pcie_port *pp); +void dw_pcie_msi_cfg_store(struct pcie_port *pp); +void dw_pcie_msi_cfg_restore(struct pcie_port *pp); int dw_pcie_link_up(struct pcie_port *pp); void dw_pcie_setup_rc(struct pcie_port *pp); int dw_pcie_host_init(struct pcie_port *pp);