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[U-Boot,1/2] mmc: fsl_esdhc: Update esdhc driver for iMX6SX

Message ID 1413191816-28236-1-git-send-email-B37916@freescale.com
State Changes Requested
Delegated to: Stefano Babic
Headers show

Commit Message

Ye.Li Oct. 13, 2014, 9:16 a.m. UTC 
The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0
on iMX6SX. So the fsl_esdhc driver must update to set the register,
otherwise no state can be detected.

Signed-off-by: Ye.Li <B37916@freescale.com>
---
 drivers/mmc/fsl_esdhc.c |   13 +++++++++++++
 1 files changed, 13 insertions(+), 0 deletions(-)

Comments

Otavio Salvador Oct. 13, 2014, 2:30 p.m. UTC | #1 
On Mon, Oct 13, 2014 at 6:16 AM, Ye.Li <B37916@freescale.com> wrote:
> The reset value of "uSDHCx_INT_STATUS_EN" register is changed to 0
> on iMX6SX. So the fsl_esdhc driver must update to set the register,
> otherwise no state can be detected.
>
> Signed-off-by: Ye.Li <B37916@freescale.com>

This patch seems to do more than described on the commit log, please split it.

> ---
>  drivers/mmc/fsl_esdhc.c |   13 +++++++++++++
>  1 files changed, 13 insertions(+), 0 deletions(-)
>
> diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
> index 97d0389..9c8a8d4 100644
> --- a/drivers/mmc/fsl_esdhc.c
> +++ b/drivers/mmc/fsl_esdhc.c
> @@ -23,6 +23,11 @@
>
>  DECLARE_GLOBAL_DATA_PTR;
>
> +#define SDHCI_IRQ_EN_BITS              (IRQSTATEN_CC | IRQSTATEN_TC | \
> +                               IRQSTATEN_CINT | \
> +                               IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
> +                               IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE)
> +
>  struct fsl_esdhc {
>         uint    dsaddr;         /* SDMA system address register */
>         uint    blkattr;        /* Block attributes register */
> @@ -492,8 +497,15 @@ static int esdhc_init(struct mmc *mmc)
>         /* Set the initial clock speed */
>         mmc_set_clock(mmc, 400000);
>
> +#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
> +       /* Enable the BRR and BWR bits in IRQSTAT */
> +       esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_DINT);
> +       esdhc_setbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
> +#else
>         /* Disable the BRR and BWR bits in IRQSTAT */
>         esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
> +       esdhc_setbits32(&regs->irqstaten, IRQSTATEN_DINT);
> +#endif
>
>         /* Put the PROCTL reg back to the default */
>         esdhc_write32(&regs->proctl, PROCTL_INIT);
> @@ -558,6 +570,7 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
>         esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
>                                 | SYSCTL_IPGEN | SYSCTL_CKEN);
>
> +       writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
>         memset(&cfg->cfg, 0, sizeof(cfg->cfg));
>
>         voltage_caps = 0;
> --
> 1.7.4.1
>
> _______________________________________________
> U-Boot mailing list
> U-Boot@lists.denx.de
> http://lists.denx.de/mailman/listinfo/u-boot
diff mbox

Patch

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index 97d0389..9c8a8d4 100644
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -23,6 +23,11 @@ 
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#define SDHCI_IRQ_EN_BITS		(IRQSTATEN_CC | IRQSTATEN_TC | \
+				IRQSTATEN_CINT | \
+				IRQSTATEN_CTOE | IRQSTATEN_CCE | IRQSTATEN_CEBE | \
+				IRQSTATEN_CIE | IRQSTATEN_DTOE | IRQSTATEN_DCE | IRQSTATEN_DEBE)
+
 struct fsl_esdhc {
 	uint    dsaddr;		/* SDMA system address register */
 	uint    blkattr;	/* Block attributes register */
@@ -492,8 +497,15 @@  static int esdhc_init(struct mmc *mmc)
 	/* Set the initial clock speed */
 	mmc_set_clock(mmc, 400000);
 
+#ifdef CONFIG_SYS_FSL_ESDHC_USE_PIO
+	/* Enable the BRR and BWR bits in IRQSTAT */
+	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_DINT);
+	esdhc_setbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+#else
 	/* Disable the BRR and BWR bits in IRQSTAT */
 	esdhc_clrbits32(&regs->irqstaten, IRQSTATEN_BRR | IRQSTATEN_BWR);
+	esdhc_setbits32(&regs->irqstaten, IRQSTATEN_DINT);
+#endif
 
 	/* Put the PROCTL reg back to the default */
 	esdhc_write32(&regs->proctl, PROCTL_INIT);
@@ -558,6 +570,7 @@  int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
 	esdhc_setbits32(&regs->sysctl, SYSCTL_PEREN | SYSCTL_HCKEN
 				| SYSCTL_IPGEN | SYSCTL_CKEN);
 
+	writel(SDHCI_IRQ_EN_BITS, &regs->irqstaten);
 	memset(&cfg->cfg, 0, sizeof(cfg->cfg));
 
 	voltage_caps = 0;