difference for this change, but adds some background. Since the ranges
declaration is beyond 80 columns the comments added are lined up with
the entries and when viewed as 80 column will wrap. If you have
suggestions on correcting this I will implement.
Thanks,
-Curtis
The stanza for PCI was copied from Bamboo which has four PCI
slots; Yosemite only has one PCI slot which is mapped to
IDSEL 12, ADDR 22, IRQ2 Vector 25, INTA.
Signed-off-by: Curtis Wald <cwald@watchguardvideo.com>
---
arch/powerpc/boot/dts/yosemite.dts | 17 +++++------------
1 files changed, 5 insertions(+), 12 deletions(-)
b/arch/powerpc/boot/dts/yosemite.dts
@@ -276,27 +276,19 @@
* later cannot be changed. Chip supports a second
* IO range but we don't use it for now
*/
+
+ /* u32 u64 u64
u64 */
+ /* pci_space pci_addr cpu_addr
size */
ranges = <0x02000000 0x00000000 0xa0000000 0x00000000 0xa0000000
0x00000000 0x20000000
0x01000000 0x00000000 0x00000000 0x00000000 0xe8000000
0x00000000 0x00010000>;
/* Inbound 2GB range starting at 0 */
dma-ranges = <0x42000000 0x0 0x0 0x0 0x0 0x0 0x80000000>;
- /* Bamboo has all 4 IRQ pins tied together per slot */
interrupt-map-mask = <0xf800 0x0 0x0 0x0>;
interrupt-map = <
- /* IDSEL 1 */
- 0x800 0x0 0x0 0x0 &UIC0 0x1c 0x8
-
- /* IDSEL 2 */
- 0x1000 0x0 0x0 0x0 &UIC0 0x1b 0x8
-
- /* IDSEL 3 */
- 0x1800 0x0 0x0 0x0 &UIC0 0x1a 0x8
-
- /* IDSEL 4 */
- 0x2000 0x0 0x0 0x0 &UIC0 0x19 0x8
+ /* IDSEL 12, ADDR 22, INTA, IRQ2 = Vector 25, 0x19 */
Josh, Here is a resend of the Yosemite.dts patch, deleting tabs and spaces in the IDSEL section that should look better when viewing as 80 column. The comments added before the ranges declaration provides info on the array element as processed by the kernel - there is no runtime + 0x6000 0x0 0x0 0x0 &UIC0 0x19 0x8 >; }; };