diff mbox

[U-Boot] board/BuR: fix pinmux for MII Ethernet Interface

Message ID 1412314215-19056-1-git-send-email-oe5hpm@oevsv.at
State Accepted
Delegated to: Tom Rini
Headers show

Commit Message

Hannes Schmelzer Oct. 3, 2014, 5:30 a.m. UTC 
The lines COL (collision detect) and CRS (carrier sense) needs to be connected
and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
interface.

Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
Cc: Tom Rini <trini@ti.com>
---
 board/BuR/kwb/mux.c     |    2 ++
 board/BuR/tseries/mux.c |    3 +++
 2 files changed, 5 insertions(+)

Comments

Tom Rini Oct. 10, 2014, 2:42 p.m. UTC | #1 
On Fri, Oct 03, 2014 at 07:30:15AM +0200, Hannes Petermaier wrote:

> The lines COL (collision detect) and CRS (carrier sense) needs to be connected
> and muxed to the CPSW MAC for a proper function in half-duplex Mode of the
> interface.
> 
> Signed-off-by: Hannes Petermaier <oe5hpm@oevsv.at>
> Cc: Tom Rini <trini@ti.com>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/board/BuR/kwb/mux.c b/board/BuR/kwb/mux.c
index 3a9ad42..10a1073 100644
--- a/board/BuR/kwb/mux.c
+++ b/board/BuR/kwb/mux.c
@@ -103,6 +103,8 @@  static struct module_pin_mux i2c0_pin_mux[] = {
 };
 
 static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
 	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
 	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
 	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
diff --git a/board/BuR/tseries/mux.c b/board/BuR/tseries/mux.c
index b526c82..3ac0208 100644
--- a/board/BuR/tseries/mux.c
+++ b/board/BuR/tseries/mux.c
@@ -64,6 +64,8 @@  static struct module_pin_mux spi0_pin_mux[] = {
 };
 
 static struct module_pin_mux mii1_pin_mux[] = {
+	{OFFSET(mii1_crs), MODE(0) | RXACTIVE},		/* MII1_CRS */
+	{OFFSET(mii1_col), MODE(0) | RXACTIVE},		/* MII1_COL */
 	{OFFSET(mii1_rxerr), MODE(0) | RXACTIVE},	/* MII1_RXERR */
 	{OFFSET(mii1_txen), MODE(0)},			/* MII1_TXEN */
 	{OFFSET(mii1_rxdv), MODE(0) | RXACTIVE},	/* MII1_RXDV */
@@ -96,6 +98,7 @@  static struct module_pin_mux mii2_pin_mux[] = {
 	{OFFSET(gpmc_a10), MODE(1) | RXACTIVE},	/* MII2_RXD1 */
 	{OFFSET(gpmc_a11), MODE(1) | RXACTIVE},	/* MII2_RXD0 */
 	{OFFSET(gpmc_wpn), (MODE(1) | RXACTIVE)},/* MII2_RXERR */
+	{OFFSET(gpmc_wait0), (MODE(1) | RXACTIVE | PULLUP_EN)},
 						/*
 						 * MII2_CRS is shared with
 						 * NAND_WAIT0