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[U-Boot,v2] powerpc/mpc85xx: SECURE BOOT - Bypass PAMU in case of secure boot

Message ID 1411970733-11517-1-git-send-email-ruchika.gupta@freescale.com
State Accepted
Delegated to: York Sun
Headers show

Commit Message

Ruchika Gupta Sept. 29, 2014, 6:05 a.m. UTC 
By default, PAMU's (IOMMU) are enabled in case of secure boot.
Disable/bypass them , once the control reached the bootloader.

For non-secure boot, PAMU's are already bypassed in the default
SoC configuration

Signed-off-by: Ruchika Gupta <ruchika.gupta@freescale.com>
---
Changes from v1:
PAMU is available only in platforms with CORENET.
Moved the changes under #define CONFIG_FSL_CORENET
to fix build issues for non-corenet platforms

 arch/powerpc/cpu/mpc85xx/cpu_init.c   | 9 ++++++++-
 arch/powerpc/include/asm/immap_85xx.h | 1 +
 2 files changed, 9 insertions(+), 1 deletion(-)
diff mbox

Patch

diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c
index 21c3194..c522625 100644
--- a/arch/powerpc/cpu/mpc85xx/cpu_init.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c
@@ -424,7 +424,8 @@  ulong cpu_init_f(void)
 {
 	ulong flag = 0;
 	extern void m8560_cpm_reset (void);
-#ifdef CONFIG_SYS_DCSRBAR_PHYS
+#if defined(CONFIG_SYS_DCSRBAR_PHYS) || \
+	(defined(CONFIG_SECURE_BOOT) && defined(CONFIG_FSL_CORENET))
 	ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 #endif
 #if defined(CONFIG_SECURE_BOOT)
@@ -456,6 +457,12 @@  ulong cpu_init_f(void)
 #if defined(CONFIG_SYS_CPC_REINIT_F)
 	disable_cpc_sram();
 #endif
+
+#if defined(CONFIG_FSL_CORENET)
+	/* Put PAMU in bypass mode */
+	out_be32(&gur->pamubypenr, FSL_CORENET_PAMU_BYPASS);
+#endif
+
 #endif
 
 #ifdef CONFIG_CPM2
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 88c1e08..0264523 100644
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -1912,6 +1912,7 @@  defined(CONFIG_PPC_T1020) || defined(CONFIG_PPC_T1022)
 	u8	res24[64];
 	u32	pblsr;		/* Preboot loader status */
 	u32	pamubypenr;	/* PAMU bypass enable */
+#define FSL_CORENET_PAMU_BYPASS		0xffff0000
 	u32	dmacr1;		/* DMA control */
 	u8	res25[4];
 	u32	gensr1;		/* General status */