From patchwork Wed Nov 25 17:04:29 2009 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartlomiej Zolnierkiewicz X-Patchwork-Id: 39396 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.176.167]) by ozlabs.org (Postfix) with ESMTP id 26135100AAA for ; Thu, 26 Nov 2009 04:28:42 +1100 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1759191AbZKYRFN (ORCPT ); Wed, 25 Nov 2009 12:05:13 -0500 Received: (majordomo@vger.kernel.org) by vger.kernel.org id S1759181AbZKYRFK (ORCPT ); Wed, 25 Nov 2009 12:05:10 -0500 Received: from mail-fx0-f213.google.com ([209.85.220.213]:53682 "EHLO mail-fx0-f213.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1759033AbZKYRFH (ORCPT ); Wed, 25 Nov 2009 12:05:07 -0500 Received: by mail-fx0-f213.google.com with SMTP id 5so7204645fxm.28 for ; Wed, 25 Nov 2009 09:05:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=gamma; h=domainkey-signature:received:received:from:to:cc:date:message-id :in-reply-to:references:subject; bh=ysHb4dCaKwbZPBUFhiGyCryKgKjM0q0VPne7c6esD9U=; b=HQNodc2m4Ido6fkHNBjZKuoKUVQskDmArsj0cxJlg7QM9fTMt37dPt8okiuLbl2jEJ CZlG179oKOKc/5Ee1fhoE/5Yi7abwBw5rca4y+j74Yf/a4nsLMJkwSlFRGDi1iv/vCKD arF/aJzR67KlJaWoBZLoVEl5C1PhXV+S5D61s= DomainKey-Signature: a=rsa-sha1; c=nofws; d=gmail.com; s=gamma; h=from:to:cc:date:message-id:in-reply-to:references:subject; b=AuBxNdJh64+t4PKjnpg9mkuRzGpCl3BajUix+3qwIycARWMVOoel0vV+SHt9upD8P4 05SvU0NaFVhbSjwBSvJ9yZ4jg1nvmM+i8rJVvVswWsUui7RtVAx6NiAWam5GmPhSjNAw JDNWN6zX09ElV+CWSA1zzn9ZsQ93pLU+N0WOw= Received: by 10.216.86.129 with SMTP id w1mr2548635wee.145.1259168713052; Wed, 25 Nov 2009 09:05:13 -0800 (PST) Received: from ?127.0.0.1? (chello089079027028.chello.pl [89.79.27.28]) by mx.google.com with ESMTPS id q9sm14669625gve.0.2009.11.25.09.05.11 (version=TLSv1/SSLv3 cipher=RC4-MD5); Wed, 25 Nov 2009 09:05:12 -0800 (PST) From: Bartlomiej Zolnierkiewicz To: linux-ide@vger.kernel.org Cc: Bartlomiej Zolnierkiewicz , linux-kernel@vger.kernel.org Date: Wed, 25 Nov 2009 18:04:29 +0100 Message-Id: <20091125170429.5446.72349.sendpatchset@localhost> In-Reply-To: <20091125170218.5446.13513.sendpatchset@localhost> References: <20091125170218.5446.13513.sendpatchset@localhost> Subject: [PATCH 18/86] pata_efar: unify code for programming PIO and MWDMA timings Sender: linux-ide-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-ide@vger.kernel.org From: Bartlomiej Zolnierkiewicz Subject: [PATCH] pata_efar: unify code for programming PIO and MWDMA timings It results in ~10% decrease in the driver LOC count and also ~8% decrease in the driver binary size (as measured on x86-32). This change should be safe as this is how we have been doing things in IDE slc90e66 host driver for years. Signed-off-by: Bartlomiej Zolnierkiewicz --- drivers/ata/pata_efar.c | 88 +++++++++++++++--------------------------------- 1 file changed, 29 insertions(+), 59 deletions(-) -- To unsubscribe from this list: send the line "unsubscribe linux-ide" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Index: b/drivers/ata/pata_efar.c =================================================================== --- a/drivers/ata/pata_efar.c +++ b/drivers/ata/pata_efar.c @@ -68,20 +68,9 @@ static int efar_cable_detect(struct ata_ return ATA_CBL_PATA80; } -/** - * efar_set_piomode - Initialize host controller PATA PIO timings - * @ap: Port whose timings we are configuring - * @adev: Device to program - * - * Set PIO mode for device, in host controller PCI config space. - * - * LOCKING: - * None (inherited from caller). - */ - -static void efar_set_piomode (struct ata_port *ap, struct ata_device *adev) +static void efar_set_timings(struct ata_port *ap, struct ata_device *adev, + u8 pio, bool use_mwdma) { - unsigned int pio = adev->pio_mode - XFER_PIO_0; struct pci_dev *dev = to_pci_dev(ap->host->dev); u8 master_port = ap->port_no ? 0x42 : 0x40; u16 master_data; @@ -99,13 +88,18 @@ static void efar_set_piomode (struct ata { 2, 1 }, { 2, 3 }, }; - if (pio > 1) + if (pio > 1 || use_mwdma) control |= 1; /* TIME */ - if (ata_pio_need_iordy(adev)) /* PIO 3/4 require IORDY */ + if (ata_pio_need_iordy(adev) || use_mwdma) control |= 2; /* IE */ /* Intel specifies that the prefetch/posting is for disk only */ if (adev->class == ATA_DEV_ATA) control |= 4; /* PPE */ + /* If the drive MWDMA is faster than it can do PIO then + we must force PIO into PIO0 */ + if (use_mwdma && adev->pio_mode < (XFER_PIO_0 + pio)) + /* Enable DMA timing only */ + control |= 8; /* PIO cycles in PIO0 */ pci_read_config_word(dev, master_port, &master_data); @@ -134,6 +128,22 @@ static void efar_set_piomode (struct ata } /** + * efar_set_piomode - Initialize host controller PATA PIO timings + * @ap: Port whose timings we are configuring + * @adev: Device to program + * + * Set PIO mode for device, in host controller PCI config space. + * + * LOCKING: + * None (inherited from caller). + */ + +static void efar_set_piomode(struct ata_port *ap, struct ata_device *adev) +{ + efar_set_timings(ap, adev, adev->pio_mode - XFER_PIO_0, 0); +} + +/** * efar_set_dmamode - Initialize host controller PATA DMA timings * @ap: Port whose timings we are configuring * @adev: Device to program @@ -147,24 +157,14 @@ static void efar_set_piomode (struct ata static void efar_set_dmamode (struct ata_port *ap, struct ata_device *adev) { struct pci_dev *dev = to_pci_dev(ap->host->dev); - u8 master_port = ap->port_no ? 0x42 : 0x40; - u16 master_data; u8 speed = adev->dma_mode; int devid = adev->devno + 2 * ap->port_no; u8 udma_enable; - static const /* ISP RTC */ - u8 timings[][2] = { { 0, 0 }, - { 0, 0 }, - { 1, 0 }, - { 2, 1 }, - { 2, 3 }, }; - - pci_read_config_word(dev, master_port, &master_data); pci_read_config_byte(dev, 0x48, &udma_enable); if (speed >= XFER_UDMA_0) { - unsigned int udma = adev->dma_mode - XFER_UDMA_0; + unsigned int udma = speed - XFER_UDMA_0; u16 udma_timing; udma_enable |= (1 << devid); @@ -175,46 +175,16 @@ static void efar_set_dmamode (struct ata udma_timing |= udma << (4 * devid); pci_write_config_word(dev, 0x4A, udma_timing); } else { - /* - * MWDMA is driven by the PIO timings. We must also enable - * IORDY unconditionally along with TIME1. PPE has already - * been set when the PIO timing was set. - */ - unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; - unsigned int control; - u8 slave_data; + /* MWDMA is driven by the PIO timings. */ + unsigned int mwdma = speed - XFER_MW_DMA_0; const unsigned int needed_pio[3] = { XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 }; int pio = needed_pio[mwdma] - XFER_PIO_0; - control = 3; /* IORDY|TIME1 */ - - /* If the drive MWDMA is faster than it can do PIO then - we must force PIO into PIO0 */ + efar_set_timings(ap, adev, pio, 1); - if (adev->pio_mode < needed_pio[mwdma]) - /* Enable DMA timing only */ - control |= 8; /* PIO cycles in PIO0 */ - - if (adev->devno) { /* Slave */ - master_data &= 0xFF4F; /* Mask out IORDY|TIME1|DMAONLY */ - master_data |= control << 4; - pci_read_config_byte(dev, 0x44, &slave_data); - slave_data &= ap->port_no ? 0x0F : 0xF0; - /* Load the matching timing */ - slave_data |= ((timings[pio][0] << 2) | timings[pio][1]) << (ap->port_no ? 4 : 0); - pci_write_config_byte(dev, 0x44, slave_data); - } else { /* Master */ - master_data &= 0xCCF4; /* Mask out IORDY|TIME1|DMAONLY - and master timing bits */ - master_data |= control; - master_data |= - (timings[pio][0] << 12) | - (timings[pio][1] << 8); - } udma_enable &= ~(1 << devid); - pci_write_config_word(dev, master_port, master_data); } pci_write_config_byte(dev, 0x48, udma_enable); }