@@ -16,6 +16,7 @@
#include <netdev.h>
#include <fsl_mdio.h>
#include <tsec.h>
+#include <spl.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -65,6 +66,7 @@ struct cpld_data {
u8 rev2; /* Reserved */
};
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
static void convert_serdes_mux(int type, int need_reset);
void cpld_show(void)
@@ -100,11 +102,14 @@ void cpld_show(void)
in_8(&cpld_data->serdes_mux));
#endif
}
+#endif
int checkboard(void)
{
puts("Board: LS1021ATWR\n");
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
cpld_show();
+#endif
return 0;
}
@@ -213,6 +218,7 @@ int board_eth_init(bd_t *bis)
}
#endif
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
int config_serdes_mux(void)
{
struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
@@ -244,6 +250,7 @@ int config_serdes_mux(void)
return 0;
}
+#endif
int board_early_init_f(void)
{
@@ -270,13 +277,33 @@ int board_early_init_f(void)
return 0;
}
+#ifdef CONFIG_SPL_BUILD
+void board_init_f(ulong dummy)
+{
+ /* Set global data pointer */
+ gd = &gdata;
+
+ /* Clear the BSS */
+ memset(__bss_start, 0, __bss_end - __bss_start);
+
+ get_clocks();
+
+ preloader_console_init();
+
+ dram_init();
+
+ board_init_r(NULL, 0);
+}
+#endif
+
int board_init(void)
{
#ifndef CONFIG_SYS_FSL_NO_SERDES
fsl_serdes_init();
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
config_serdes_mux();
#endif
-
+#endif
return 0;
}
@@ -304,6 +331,7 @@ u16 flash_read16(void *addr)
return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
}
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
static void convert_flash_bank(char bank)
{
struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE);
@@ -486,3 +514,4 @@ U_BOOT_CMD(
" -change lane C & lane D to PCIeX2\n"
"\nWARNING: If you aren't familiar with the setting of serdes, don't try to change anything!\n"
);
+#endif
new file mode 100644
@@ -0,0 +1,13 @@
+#PBI commands
+
+09570200 ffffffff
+09570158 00000300
+09570200 00000000
+8940007c 21f47300
+
+#Configure Scratch register
+09ee0200 10000000
+#Configure alternate space
+09570158 00080000
+#Flush PBL data
+096100c0 000FFFFF
new file mode 100644
@@ -0,0 +1,14 @@
+#PBL preamble and RCW header
+aa55aa55 01ee0100
+
+#enable IFC, disable QSPI and DSPI
+#0608000a 00000000 00000000 00000000
+#20000000 00404000 60025a00 21042000
+#00200000 00000000 00000000 01038000
+#00000000 001b1200 00000000 00000000
+
+#disable IFC, enable QSPI and DSPI
+0608000a 00000000 00000000 00000000
+20000000 00407900 60025a00 21046000
+00000000 00000000 00000000 01038000
+20024800 881b1540 00000000 00000000
new file mode 100644
@@ -0,0 +1,4 @@
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
++S:CONFIG_ARM=y
++S:CONFIG_TARGET_LS1021ATWR=y
@@ -35,6 +35,40 @@
#define CONFIG_SYS_CLK_FREQ 100000000
#define CONFIG_DDR_CLK_FREQ 100000000
+#ifdef CONFIG_RAMBOOT_PBL
+#define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
+#endif
+
+#ifdef CONFIG_SD_BOOT
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
+#define CONFIG_SPL_PBL_PAD
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
+#define CONFIG_SPL_LIBCOMMON_SUPPORT
+#define CONFIG_SPL_LIBGENERIC_SUPPORT
+#define CONFIG_SPL_ENV_SUPPORT
+#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
+#define CONFIG_SPL_I2C_SUPPORT
+#define CONFIG_SPL_WATCHDOG_SUPPORT
+#define CONFIG_SPL_SERIAL_SUPPORT
+#define CONFIG_SPL_MMC_SUPPORT
+#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
+#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
+
+#define CONFIG_SPL_TEXT_BASE 0x10000000
+#define CONFIG_SPL_MAX_SIZE 0x1a000
+#define CONFIG_SPL_STACK 0x1001d000
+#define CONFIG_SPL_PAD_TO 0x1c000
+#define CONFIG_SYS_TEXT_BASE 0x82000000
+
+#define CONFIG_SYS_SPL_MALLOC_START 0x80200000
+#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
+#define CONFIG_SPL_BSS_START_ADDR 0x80100000
+#define CONFIG_SPL_BSS_MAX_SIZE 0x80000
+#define CONFIG_SYS_MONITOR_LEN 0x80000
+#define CONFIG_SYS_NO_FLASH
+#endif
+
#ifndef CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_TEXT_BASE 0x67f80000
#endif
@@ -51,6 +85,7 @@
/*
* IFC Definitions
*/
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_FSL_IFC
#define CONFIG_SYS_FLASH_BASE 0x60000000
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
@@ -93,6 +128,7 @@
#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
+#endif
/* CPLD */
@@ -225,7 +261,12 @@
#define CONFIG_CMDLINE_TAG
#define CONFIG_CMDLINE_EDITING
+
+#if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_QSPI_BOOT)
#define CONFIG_CMD_IMLS
+#else
+#undef CONFIG_CMD_IMLS
+#endif
#define CONFIG_HWCONFIG
#define HWCONFIG_BUFFER_SIZE 128
@@ -272,17 +313,28 @@
#define CONFIG_SYS_INIT_SP_ADDR \
(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
+#else
#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
+#endif
/*
* Environment
*/
#define CONFIG_ENV_OVERWRITE
+#if defined(CONFIG_SD_BOOT)
+#define CONFIG_ENV_OFFSET (1024 * 1024)
+#define CONFIG_ENV_IS_IN_MMC
+#define CONFIG_SYS_MMC_ENV_DEV 0
+#define CONFIG_ENV_SIZE 0x20000
+#else
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE 0x20000
#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
+#endif
#define CONFIG_OF_LIBFDT
#define CONFIG_OF_BOARD_SETUP