@@ -716,8 +716,9 @@ Returns:
}
+STATIC
VOID
-PciInitialization (
+PciInitializationPIIX (
)
{
//
@@ -765,6 +766,55 @@ PciInitialization (
}
+STATIC
+VOID
+PciInitializationQ35 (
+ )
+{
+ //
+ // Bus 0, Device 0x1f, Function 0 - LPC Bridge: Initialize PIC IRQ routing
+ //
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x60), 0x0a); // LNKA routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x61), 0x0a); // LNKB routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x62), 0x0b); // LNKC routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x63), 0x0b); // LNKD routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x68), 0x0a); // LNKE routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x69), 0x0a); // LNKF routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6a), 0x0b); // LNKG routing target
+ PciWrite8 (PCI_LIB_ADDRESS (0, 0x1f, 0, 0x6b), 0x0b); // LNKH routing target
+}
+
+
+//
+// Distinguish between Q35 and PIIX host bridges
+//
+#define PCI_DEVICE_ID_INTEL_82441 0x1237 // DID value for PIIX4
+#define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29C0 // DID value for Q35
+
+#define HOSTBRIDGE_DID PCI_LIB_ADDRESS (0, 0, 0, 0x02)
+#define IS_Q35_HOSTBRIDGE (PciRead16 (HOSTBRIDGE_DID) == PCI_DEVICE_ID_INTEL_Q35_MCH)
+
+
+VOID
+PciInitialization (
+ )
+{
+ if (IS_Q35_HOSTBRIDGE) {
+ PciInitializationQ35 ();
+ } else {
+ PciInitializationPIIX ();
+ }
+}
+
+
+//
+// Locate PMCNTRL register (0x40) on the appropriate (Q35 vs. PIIX) host bridge
+//
+#define PMCNTRL_PIIX PCI_LIB_ADDRESS (0, 1, 3, 0x40)
+#define PMCNTRL_Q35 PCI_LIB_ADDRESS (0, 0x1f, 0, 0x40)
+#define PMCNTRL (IS_Q35_HOSTBRIDGE ? PMCNTRL_Q35 : PMCNTRL_PIIX)
+
+
VOID
AcpiInitialization (
VOID
@@ -773,7 +823,7 @@ AcpiInitialization (
//
// Set ACPI SCI_EN bit in PMCNTRL
//
- IoOr16 ((PciRead32 (PCI_LIB_ADDRESS (0, 1, 3, 0x40)) & ~BIT0) + 4, BIT0);
+ IoOr16 ((PciRead32 (PMCNTRL) & ~BIT0) + 4, BIT0);
}