@@ -155,7 +155,7 @@
BUILTIN_VSD_HSI (BINOP, sqdmull, 0)
BUILTIN_VSD_HSI (TERNOP, sqdmull_lane, 0)
- BUILTIN_VD_HSI (TERNOP, sqdmull_laneq, 0)
+ BUILTIN_VSD_HSI (TERNOP, sqdmull_laneq, 0)
BUILTIN_VD_HSI (BINOP, sqdmull_n, 0)
BUILTIN_VQ_HSI (BINOP, sqdmull2, 0)
BUILTIN_VQ_HSI (TERNOP, sqdmull2_lane, 0)
@@ -3398,7 +3398,7 @@ (define_expand "aarch64_sqdmull_lane<mod
(define_expand "aarch64_sqdmull_laneq<mode>"
[(match_operand:<VWIDE> 0 "register_operand" "=w")
- (match_operand:VD_HSI 1 "register_operand" "w")
+ (match_operand:VSD_HSI 1 "register_operand" "w")
(match_operand:<VCONQ> 2 "register_operand" "<vwx>")
(match_operand:SI 3 "immediate_operand" "i")]
"TARGET_SIMD"
@@ -19420,16 +19420,28 @@ vqdmullh_lane_s16 (int16_t __a, int16x4_t __b, const int __c)
return __builtin_aarch64_sqdmull_lanehi (__a, __b, __c);
}
+__extension__ static __inline int32_t __attribute__ ((__always_inline__))
+vqdmullh_laneq_s16 (int16_t __a, int16x8_t __b, const int __c)
+{
+ return __builtin_aarch64_sqdmull_laneqhi (__a, __b, __c);
+}
+
__extension__ static __inline int64_t __attribute__ ((__always_inline__))
vqdmulls_s32 (int32_t __a, int32_t __b)
{
return __builtin_aarch64_sqdmullsi (__a, __b);
}
-__extension__ static __inline int64x1_t __attribute__ ((__always_inline__))
+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
vqdmulls_lane_s32 (int32_t __a, int32x2_t __b, const int __c)
{
- return (int64x1_t) {__builtin_aarch64_sqdmull_lanesi (__a, __b, __c)};
+ return __builtin_aarch64_sqdmull_lanesi (__a, __b, __c);
+}
+
+__extension__ static __inline int64_t __attribute__ ((__always_inline__))
+vqdmulls_laneq_s32 (int32_t __a, int32x4_t __b, const int __c)
+{
+ return __builtin_aarch64_sqdmull_laneqsi (__a, __b, __c);
}
/* vqmovn */
@@ -501,7 +501,7 @@ test_vqdmulls_s32 (int32_t a, int32_t b)
/* { dg-final { scan-assembler-times "\\tsqdmull\\td\[0-9\]+, s\[0-9\]+, v" 1 } } */
-int64x1_t
+int64_t
test_vqdmulls_lane_s32 (int32_t a, int32x2_t b)
{
return vqdmulls_lane_s32 (a, b, 1);
new file mode 100644
@@ -0,0 +1,15 @@
+/* Test the vqdmullh_laneq_s16 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int32_t
+t_vqdmullh_laneq_s16 (int16_t a, int16x8_t b)
+{
+ return vqdmullh_laneq_s16 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[sS\]\[0-9\]+, ?\[hH\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[hH\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */
@@ -5,7 +5,7 @@
#include "arm_neon.h"
-int64x1_t
+int64_t
t_vqdmulls_lane_s32 (int32_t a, int32x2_t b)
{
return vqdmulls_lane_s32 (a, b, 0);
new file mode 100644
@@ -0,0 +1,15 @@
+/* Test the vqdmulls_laneq_s32 AArch64 SIMD intrinsic. */
+
+/* { dg-do compile } */
+/* { dg-options "-save-temps -O3 -fno-inline" } */
+
+#include "arm_neon.h"
+
+int64_t
+t_vqdmulls_laneq_s32 (int32_t a, int32x4_t b)
+{
+ return vqdmulls_laneq_s32 (a, b, 0);
+}
+
+/* { dg-final { scan-assembler-times "sqdmull\[ \t\]+\[dD\]\[0-9\]+, ?\[sS\]\[0-9\]+, ?\[vV\]\[0-9\]+\.\[sS\]\\\[0\\\]\n" 1 } } */
+/* { dg-final { cleanup-saved-temps } } */