| Message ID | 1411481312-9929-5-git-send-email-sr@denx.de |
|---|---|
| State | Superseded |
| Delegated to: | Marek Vasut |
| Headers | show |
On Tuesday, September 23, 2014 at 04:08:32 PM, Stefan Roese wrote: > The Cadence SPI driver currently has some problems when the dcache is > enabled. As a work-around until this problem is fixed in the SPI driver, > lets not enable the dcache on the socfpga platforms. As its also done in > the rocketboards version. > > Signed-off-by: Stefan Roese <sr@denx.de> > Cc: Chin Liang See <clsee@altera.com> > Cc: Dinh Nguyen <dinguyen@altera.com> > Cc: Vince Bridgers <vbridger@altera.com> > Cc: Marek Vasut <marex@denx.de> > Cc: Pavel Machek <pavel@denx.de> > Cc: Michael Trimarchi <michael@amarulasolutions.com> > --- > board/altera/socfpga/socfpga_cyclone5.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/board/altera/socfpga/socfpga_cyclone5.c > b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644 > --- a/board/altera/socfpga/socfpga_cyclone5.c > +++ b/board/altera/socfpga/socfpga_cyclone5.c > @@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev) > int board_init(void) > { > icache_enable(); > +#if 0 // test-only: disable dcache for now as it causes problems with the > SPI driver dcache_enable(); > +#endif This means the DMA code in cadence driver is not flushing/invalidating cache as it should. Are you planning to fix it proper eventually? But this is really a good thing that you found this out! That's an important information, thanks! Best regards, Marek Vasut
On 23.09.2014 16:32, Marek Vasut wrote: >> diff --git a/board/altera/socfpga/socfpga_cyclone5.c >> b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644 >> --- a/board/altera/socfpga/socfpga_cyclone5.c >> +++ b/board/altera/socfpga/socfpga_cyclone5.c >> @@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev) >> int board_init(void) >> { >> icache_enable(); >> +#if 0 // test-only: disable dcache for now as it causes problems with the >> SPI driver dcache_enable(); >> +#endif > > This means the DMA code in cadence driver is not flushing/invalidating cache > as it should. I am aware of this. Caching related issues are definitely not new to me. ;) I didn't spot any DMA controller related code in the driver. Only some FIFO stuff which is most likely the problematic code part. But since I've no deeper insight in this IP core right now, I just wanted to offer this info to others for now. > Are you planning to fix it proper eventually? Not right now, sorry. As I explained in my cover letter, I have to move to other projects. At least for a few days. > But this is really a good thing that you found this out! That's an important > information, thanks! Yes, thats exactly why I posted it in this stage. Thanks, Stefan
Hi On Tue, Sep 23, 2014 at 5:20 PM, Stefan Roese <sr@denx.de> wrote: > On 23.09.2014 16:32, Marek Vasut wrote: >>> >>> diff --git a/board/altera/socfpga/socfpga_cyclone5.c >>> b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644 >>> --- a/board/altera/socfpga/socfpga_cyclone5.c >>> +++ b/board/altera/socfpga/socfpga_cyclone5.c >>> @@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev) >>> int board_init(void) >>> { >>> icache_enable(); >>> +#if 0 // test-only: disable dcache for now as it causes problems with >>> the >>> SPI driver dcache_enable(); >>> +#endif >> >> >> This means the DMA code in cadence driver is not flushing/invalidating >> cache >> as it should. > > > I am aware of this. Caching related issues are definitely not new to me. ;) > > I didn't spot any DMA controller related code in the driver. Only some FIFO > stuff which is most likely the problematic code part. But since I've no > deeper insight in this IP core right now, I just wanted to offer this info > to others for now. > >> Are you planning to fix it proper eventually? > > > Not right now, sorry. As I explained in my cover letter, I have to move to > other projects. At least for a few days. > me too ;). I don't have any fpga on my desk right now (maybe in 3 weeks) >> But this is really a good thing that you found this out! That's an >> important >> information, thanks! > > > Yes, thats exactly why I posted it in this stage. > I'm really happy that start to work ;) Michael > Thanks, > Stefan >
diff --git a/board/altera/socfpga/socfpga_cyclone5.c b/board/altera/socfpga/socfpga_cyclone5.c index 10f15e0..3f19d89 100644 --- a/board/altera/socfpga/socfpga_cyclone5.c +++ b/board/altera/socfpga/socfpga_cyclone5.c @@ -76,7 +76,9 @@ int board_phy_config(struct phy_device *phydev) int board_init(void) { icache_enable(); +#if 0 // test-only: disable dcache for now as it causes problems with the SPI driver dcache_enable(); +#endif /* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
The Cadence SPI driver currently has some problems when the dcache is enabled. As a work-around until this problem is fixed in the SPI driver, lets not enable the dcache on the socfpga platforms. As its also done in the rocketboards version. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Chin Liang See <clsee@altera.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Vince Bridgers <vbridger@altera.com> Cc: Marek Vasut <marex@denx.de> Cc: Pavel Machek <pavel@denx.de> Cc: Michael Trimarchi <michael@amarulasolutions.com> --- board/altera/socfpga/socfpga_cyclone5.c | 2 ++ 1 file changed, 2 insertions(+)