pata_hpt{37x|3x2n}: fix timing register masks

Submitted by Sergei Shtylyov on Nov. 24, 2009, 8:15 p.m.

Details

Message ID 200911242315.52826.sshtylyov@ru.mvista.com
State Not Applicable
Delegated to: David Miller
Headers show

Commit Message

Sergei Shtylyov Nov. 24, 2009, 8:15 p.m.
These drivers inherited from the older 'hpt366' IDE driver the buggy timing
register masks in their set_piomode() metods. As a result, too low command
cycle active time is programmed for slow PIO modes.  Quite fortunately, it's
later "fixed up" by the set_dmamode() methods which also "helpfully" reprogram
the command timings, usually to PIO mode 4.

However, the drivers added some breakage of their own too:  the bit that they
set/clear to control the FIFO is wrong -- it's actually the MSB of the command
cycle setup time; setting it in DMA mode is also wrong as this bit is only for
PIO actually...

Fix all this and bump the drivers' versions, accounting for recenjt patches
that forgot to do it...

Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: stable@kernel.org

---
The patch is against the recent Linus' tree. It's intended to go into all
stable kernels starting with 2.6.19, when the PATA drivers were first merged.

 drivers/ata/pata_hpt37x.c  |   13 ++++++-------
 drivers/ata/pata_hpt3x2n.c |   13 ++++++-------
 2 files changed, 12 insertions(+), 14 deletions(-)


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Comments

Alan Cox Nov. 24, 2009, 9:20 p.m.
On Wed, 25 Nov 2009 00:15:52 +0400
Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:

> These drivers inherited from the older 'hpt366' IDE driver the buggy timing
> register masks in their set_piomode() metods. As a result, too low command
> cycle active time is programmed for slow PIO modes.  Quite fortunately, it's
> later "fixed up" by the set_dmamode() methods which also "helpfully" reprogram
> the command timings, usually to PIO mode 4.
> 
> However, the drivers added some breakage of their own too:  the bit that they
> set/clear to control the FIFO is wrong -- it's actually the MSB of the command
> cycle setup time; setting it in DMA mode is also wrong as this bit is only for
> PIO actually...
> 
> Fix all this and bump the drivers' versions, accounting for recenjt patches
> that forgot to do it...
> 
> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>

Acked-by: Alan Cox <alan@linux.intel.com>
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Bartlomiej Zolnierkiewicz Nov. 26, 2009, 8:51 p.m.
On Tuesday 24 November 2009 10:20:06 pm Alan Cox wrote:
> On Wed, 25 Nov 2009 00:15:52 +0400
> Sergei Shtylyov <sshtylyov@ru.mvista.com> wrote:
> 
> > These drivers inherited from the older 'hpt366' IDE driver the buggy timing
> > register masks in their set_piomode() metods. As a result, too low command
> > cycle active time is programmed for slow PIO modes.  Quite fortunately, it's
> > later "fixed up" by the set_dmamode() methods which also "helpfully" reprogram
> > the command timings, usually to PIO mode 4.
> > 
> > However, the drivers added some breakage of their own too:  the bit that they
> > set/clear to control the FIFO is wrong -- it's actually the MSB of the command
> > cycle setup time; setting it in DMA mode is also wrong as this bit is only for
> > PIO actually...
> > 
> > Fix all this and bump the drivers' versions, accounting for recenjt patches
> > that forgot to do it...

Sergei, pata_hpt37x contains another copy of ->set_{piomode,dmamode} methods
(for HPT372 and later chipsets) which also need to be updated.

> > Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
> 
> Acked-by: Alan Cox <alan@linux.intel.com>

--
Bartlomiej Zolnierkiewicz
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Sergei Shtylyov Nov. 26, 2009, 9:18 p.m.
Hello.

Bartlomiej Zolnierkiewicz wrote:

>>> These drivers inherited from the older 'hpt366' IDE driver the buggy timing
>>> register masks in their set_piomode() metods. As a result, too low command
>>> cycle active time is programmed for slow PIO modes.  Quite fortunately, it's
>>> later "fixed up" by the set_dmamode() methods which also "helpfully" reprogram
>>> the command timings, usually to PIO mode 4.
>>>
>>> However, the drivers added some breakage of their own too:  the bit that they
>>> set/clear to control the FIFO is wrong -- it's actually the MSB of the command
>>> cycle setup time; setting it in DMA mode is also wrong as this bit is only for
>>> PIO actually...
>>>
>>> Fix all this and bump the drivers' versions, accounting for recenjt patches
>>> that forgot to do it...
>>>       
>
> Sergei, pata_hpt37x contains another copy of ->set_{piomode,dmamode} methods
> (for HPT372 and later chipsets) which also need to be updated.
>   

   Oh, horror... :-(
   They also all need to be squashed together and the interrupt bit 
manipulation moved to some other place...

>>> Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
>>>       
>> Acked-by: Alan Cox <alan@linux.intel.com>
>>     
>
> --
> Bartlomiej Zolnierkiewicz
>   

MBR, Sergei


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Sergei Shtylyov Nov. 26, 2009, 9:42 p.m.
Hello, I wrote:

>>>> These drivers inherited from the older 'hpt366' IDE driver the 
>>>> buggy timing
>>>> register masks in their set_piomode() metods. As a result, too low 
>>>> command
>>>> cycle active time is programmed for slow PIO modes.  Quite 
>>>> fortunately, it's
>>>> later "fixed up" by the set_dmamode() methods which also 
>>>> "helpfully" reprogram
>>>> the command timings, usually to PIO mode 4.
>>>>
>>>> However, the drivers added some breakage of their own too:  the bit 
>>>> that they
>>>> set/clear to control the FIFO is wrong -- it's actually the MSB of 
>>>> the command
>>>> cycle setup time; setting it in DMA mode is also wrong as this bit 
>>>> is only for
>>>> PIO actually...
>>>>
>>>> Fix all this and bump the drivers' versions, accounting for recenjt 
>>>> patches
>>>> that forgot to do it...
>>>>       
>>
>> Sergei, pata_hpt37x contains another copy of ->set_{piomode,dmamode} 
>> methods
>> (for HPT372 and later chipsets) which also need to be updated.
>>   
>
>   Oh, horror... :-(
>   They also all need to be squashed together and the interrupt bit 
> manipulation moved to some other place...

   I think I'll also do use different masks for UDMA and MWDMA in order 
to not change PIO data timings when setting an UDMA mode.

MBR, Sergei


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Patch hide | download patch | download mbox

Index: linux-2.6/drivers/ata/pata_hpt37x.c
===================================================================
--- linux-2.6.orig/drivers/ata/pata_hpt37x.c
+++ linux-2.6/drivers/ata/pata_hpt37x.c
@@ -24,7 +24,7 @@ 
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt37x"
-#define DRV_VERSION	"0.6.12"
+#define DRV_VERSION	"0.6.14"
 
 struct hpt_clock {
 	u8	xfer_speed;
@@ -404,9 +404,9 @@  static void hpt370_set_piomode(struct at
 
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt37x_find_mode(ap, adev->pio_mode);
-	mode &= ~0x8000000;	/* No FIFO in PIO */
-	mode &= ~0x30070000;	/* Leave config bits alone */
-	reg &= 0x30070000;	/* Strip timing bits */
+	mode &= ~0x80000000;	/* Disable FIFO */
+	mode &= ~0x303C0000;	/* Leave config/UDMA bits alone */
+	reg &= 0x303C0000;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -438,9 +438,8 @@  static void hpt370_set_dmamode(struct at
 
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt37x_find_mode(ap, adev->dma_mode);
-	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
-	mode &= ~0xC0000000;	/* Leave config bits alone */
-	reg &= 0xC0000000;	/* Strip timing bits */
+	mode &= ~0xCE03FE00;	/* Leave config/command bits alone */
+	reg &= 0xCE03FE00;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
Index: linux-2.6/drivers/ata/pata_hpt3x2n.c
===================================================================
--- linux-2.6.orig/drivers/ata/pata_hpt3x2n.c
+++ linux-2.6/drivers/ata/pata_hpt3x2n.c
@@ -25,7 +25,7 @@ 
 #include <linux/libata.h>
 
 #define DRV_NAME	"pata_hpt3x2n"
-#define DRV_VERSION	"0.3.4"
+#define DRV_VERSION	"0.3.7"
 
 enum {
 	HPT_PCI_FAST	=	(1 << 31),
@@ -185,9 +185,9 @@  static void hpt3x2n_set_piomode(struct a
 
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt3x2n_find_mode(ap, adev->pio_mode);
-	mode &= ~0x8000000;	/* No FIFO in PIO */
-	mode &= ~0x30070000;	/* Leave config bits alone */
-	reg &= 0x30070000;	/* Strip timing bits */
+	mode &= ~0x80000000;	/* Disable FIFO */
+	mode &= ~0x303C0000;	/* Leave config/UDMA bits alone */
+	reg &= 0x303C0000;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }
 
@@ -218,9 +218,8 @@  static void hpt3x2n_set_dmamode(struct a
 
 	pci_read_config_dword(pdev, addr1, &reg);
 	mode = hpt3x2n_find_mode(ap, adev->dma_mode);
-	mode |= 0x8000000;	/* FIFO in MWDMA or UDMA */
-	mode &= ~0xC0000000;	/* Leave config bits alone */
-	reg &= 0xC0000000;	/* Strip timing bits */
+	mode &= ~0xCE03FE00;	/* Leave config/command bits alone */
+	reg &= 0xCE03FE00;	/* Strip timing bits */
 	pci_write_config_dword(pdev, addr1, reg | mode);
 }