@@ -1292,6 +1292,28 @@ static void port_clear(AHCIState *ahci, uint8_t px)
qmemset(ahci->port[px].fb, 0x00, 0x100);
}
+/**
+ * Check a port for errors.
+ */
+static void port_check_error(AHCIState *ahci, uint8_t px)
+{
+ uint32_t reg;
+
+ /* The upper 9 bits of the IS register all indicate errors. */
+ reg = PX_RREG(px, AHCI_PX_IS);
+ reg >>= 23;
+ g_assert_cmphex(reg, ==, 0);
+
+ /* The Sata Error Register should be empty. */
+ reg = PX_RREG(px, AHCI_PX_SERR);
+ g_assert_cmphex(reg, ==, 0);
+
+ /* The TFD also has two error sections. */
+ reg = PX_RREG(px, AHCI_PX_TFD);
+ ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
+ ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
+}
+
/* Get the #cx'th command of port #px. */
static void get_command_header(AHCIState *ahci, uint8_t px,
uint8_t cx, AHCICommand *cmd)
@@ -1523,6 +1545,7 @@ static void ahci_test_identify(AHCIState *ahci)
while (BITSET(PX_RREG(i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
usleep(50);
}
+ port_check_error(ahci, i);
/* Check for expected interrupts */
reg = PX_RREG(i, AHCI_PX_IS);
@@ -1535,13 +1558,6 @@ static void ahci_test_identify(AHCIState *ahci)
PX_WREG(i, AHCI_PX_IS, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
- /* Check for errors. */
- reg = PX_RREG(i, AHCI_PX_SERR);
- g_assert_cmphex(reg, ==, 0);
- reg = PX_RREG(i, AHCI_PX_TFD);
- ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
- ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
-
/* Investigate the CMD, assert that we read 512 bytes */
get_command_header(ahci, i, cx, &cmd);
g_assert_cmphex(512, ==, cmd.prdbc);
port_check-error checks a given port's error registers and asserts that everything from the port-level view is still OK. Signed-off-by: John Snow <jsnow@redhat.com> --- tests/ahci-test.c | 30 +++++++++++++++++++++++------- 1 file changed, 23 insertions(+), 7 deletions(-)