| Message ID | 541AD3E4.2030200@arm.com |
|---|---|
| State | New |
| Headers | show |
On Thu, Sep 18, 2014 at 2:45 PM, Alan Lawrence <alan.lawrence@arm.com> wrote: > The previous patch broke aarch64_be by redefining VEC_RSHIFT_EXPR / > vec_shr_optab to always shift the vector towards gcc's element 0. This fixes > aarch64_be to do that. > > check-gcc on aarch64-none-elf (no changes) and aarch64_be-none-elf (fixes > all regressions produced by previous patch, i.e. no regressions from before > redefining vec_shr). Using vector permutes would have avoided this I guess? Richard. > > gcc/ChangeLog: > > * config/aarch64/aarch64-simd.md (vec_shr_<mode> *2): Fix bigendian. > >
diff --git a/gcc/config/aarch64/aarch64-simd.md b/gcc/config/aarch64/aarch64-simd.md index 3fcf809113d73b37a95653b8c2be432478d2bc1e..e45eddbda7528cfbb4b0953b2c9934c5408d2f6d 100644 --- a/gcc/config/aarch64/aarch64-simd.md +++ b/gcc/config/aarch64/aarch64-simd.md @@ -776,7 +776,12 @@ (lshiftrt:VD (match_operand:VD 1 "register_operand" "w") (match_operand:SI 2 "immediate_operand" "i")))] "TARGET_SIMD" - "ushr %d0, %d1, %2" + { + if (BYTES_BIG_ENDIAN) + return "ushl %d0, %d1, %2"; + else + return "ushr %d0, %d1, %2"; + } [(set_attr "type" "neon_shift_imm")] ) @@ -804,6 +809,14 @@ DONE; } + if (BYTES_BIG_ENDIAN) + { + rtx temp = operands[1]; + operands[1] = zero_reg; + zero_reg = temp; + num_bits = 128 - num_bits; + } + emit_insn (gen_aarch64_ext<mode> (operands[0], operands[1], zero_reg, GEN_INT (num_bits / elem_bits))); DONE;