diff mbox

[i386,AVX512,45/n] Add vshufpd insn patterns.

Message ID 20140918120216.GD22922@msticlxl57.ims.intel.com
State New
Headers show

Commit Message

Kirill Yukhin Sept. 18, 2014, 12:02 p.m. UTC 
Hello,
This patch supports AVX-512's vshufpd insns.

Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.

Is it ok for trunk?

gcc/
	* config/i386/sse.md
	(define_expand "avx_shufpd256<mask_expand4_name>"): Add masking.
	(define_insn "avx_shufpd256_1<mask_name>"): Ditto.
	(define_expand "sse2_shufpd<mask_expand4_name>"): Ditto.
	(define_insn "sse2_shufpd_v2df_mask"): New.

--
Thanks, K

Comments

Uros Bizjak Sept. 18, 2014, 5:18 p.m. UTC | #1 
On Thu, Sep 18, 2014 at 2:02 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Hello,
> This patch supports AVX-512's vshufpd insns.
>
> Bootstrapped.
> AVX-512* tests on top of patch-set all pass
> under simulator.
>
> Is it ok for trunk?
>
> gcc/
>         * config/i386/sse.md
>         (define_expand "avx_shufpd256<mask_expand4_name>"): Add masking.
>         (define_insn "avx_shufpd256_1<mask_name>"): Ditto.
>         (define_expand "sse2_shufpd<mask_expand4_name>"): Ditto.
>         (define_insn "sse2_shufpd_v2df_mask"): New.

OK.

Thanks,
Uros.
diff mbox

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index 9151063..9e0c0e8 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -7790,7 +7790,7 @@ 
    (set_attr "prefix" "evex")
    (set_attr "mode" "V8DF")])
 
-(define_expand "avx_shufpd256"
+(define_expand "avx_shufpd256<mask_expand4_name>"
   [(match_operand:V4DF 0 "register_operand")
    (match_operand:V4DF 1 "register_operand")
    (match_operand:V4DF 2 "nonimmediate_operand")
@@ -7798,25 +7798,28 @@ 
   "TARGET_AVX"
 {
   int mask = INTVAL (operands[3]);
-  emit_insn (gen_avx_shufpd256_1 (operands[0], operands[1], operands[2],
-				   GEN_INT (mask & 1),
-				   GEN_INT (mask & 2 ? 5 : 4),
-				   GEN_INT (mask & 4 ? 3 : 2),
-				   GEN_INT (mask & 8 ? 7 : 6)));
+  emit_insn (gen_avx_shufpd256_1<mask_expand4_name> (operands[0],
+						     operands[1],
+						     operands[2],
+						     GEN_INT (mask & 1),
+						     GEN_INT (mask & 2 ? 5 : 4),
+						     GEN_INT (mask & 4 ? 3 : 2),
+						     GEN_INT (mask & 8 ? 7 : 6)
+						     <mask_expand4_args>));
   DONE;
 })
 
-(define_insn "avx_shufpd256_1"
-  [(set (match_operand:V4DF 0 "register_operand" "=x")
+(define_insn "avx_shufpd256_1<mask_name>"
+  [(set (match_operand:V4DF 0 "register_operand" "=v")
 	(vec_select:V4DF
 	  (vec_concat:V8DF
-	    (match_operand:V4DF 1 "register_operand" "x")
-	    (match_operand:V4DF 2 "nonimmediate_operand" "xm"))
+	    (match_operand:V4DF 1 "register_operand" "v")
+	    (match_operand:V4DF 2 "nonimmediate_operand" "vm"))
 	  (parallel [(match_operand 3 "const_0_to_1_operand")
 		     (match_operand 4 "const_4_to_5_operand")
 		     (match_operand 5 "const_2_to_3_operand")
 		     (match_operand 6 "const_6_to_7_operand")])))]
-  "TARGET_AVX"
+  "TARGET_AVX && <mask_avx512vl_condition>"
 {
   int mask;
   mask = INTVAL (operands[3]);
@@ -7825,14 +7828,14 @@ 
   mask |= (INTVAL (operands[6]) - 6) << 3;
   operands[3] = GEN_INT (mask);
 
-  return "vshufpd\t{%3, %2, %1, %0|%0, %1, %2, %3}";
+  return "vshufpd\t{%3, %2, %1, %0<mask_operand7>|%0<mask_operand7>, %1, %2, %3}";
 }
   [(set_attr "type" "sseshuf")
    (set_attr "length_immediate" "1")
    (set_attr "prefix" "vex")
    (set_attr "mode" "V4DF")])
 
-(define_expand "sse2_shufpd"
+(define_expand "sse2_shufpd<mask_expand4_name>"
   [(match_operand:V2DF 0 "register_operand")
    (match_operand:V2DF 1 "register_operand")
    (match_operand:V2DF 2 "nonimmediate_operand")
@@ -7840,12 +7843,38 @@ 
   "TARGET_SSE2"
 {
   int mask = INTVAL (operands[3]);
-  emit_insn (gen_sse2_shufpd_v2df (operands[0], operands[1], operands[2],
-				GEN_INT (mask & 1),
-				GEN_INT (mask & 2 ? 3 : 2)));
+  emit_insn (gen_sse2_shufpd_v2df<mask_expand4_name> (operands[0], operands[1],
+						      operands[2], GEN_INT (mask & 1),
+						      GEN_INT (mask & 2 ? 3 : 2)
+						      <mask_expand4_args>));
   DONE;
 })
 
+(define_insn "sse2_shufpd_v2df_mask"
+  [(set (match_operand:V2DF 0 "register_operand" "=v")
+    (vec_merge:V2DF
+	  (vec_select:V2DF
+	    (vec_concat:V4DF
+	      (match_operand:V2DF 1 "register_operand" "v")
+	      (match_operand:V2DF 2 "nonimmediate_operand" "vm"))
+	    (parallel [(match_operand 3 "const_0_to_1_operand")
+		           (match_operand 4 "const_2_to_3_operand")]))
+      (match_operand:V2DF 5 "vector_move_operand" "0C")
+      (match_operand:QI 6 "register_operand" "Yk")))]
+  "TARGET_AVX512VL"
+{
+  int mask;
+  mask = INTVAL (operands[3]);
+  mask |= (INTVAL (operands[4]) - 2) << 1;
+  operands[3] = GEN_INT (mask);
+
+  return "vshufpd\t{%3, %2, %1, %0%{%6%}%N5|%0%{6%}%N5, %1, %2, %3}";
+}
+  [(set_attr "type" "sseshuf")
+   (set_attr "length_immediate" "1")
+   (set_attr "prefix" "evex")
+   (set_attr "mode" "V2DF")])
+
 ;; punpcklqdq and punpckhqdq are shorter than shufpd.
 (define_insn "avx2_interleave_highv4di<mask_name>"
   [(set (match_operand:V4DI 0 "register_operand" "=v")