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[4/4] AArch64: Add regmove_costs for Cortex-A57 and A53

Message ID 002101cfcdd3$2df88910$89e99b30$@com
State New
Headers show

Commit Message

Wilco Sept. 11, 2014, 3:15 p.m. UTC 
I've kept the integer move costs at 1 - patch attached for commit as I don't have write access.

ChangeLog:
2014-09-11  Wilco Dijkstra  <wdijkstr@arm.com>

	* gcc/config/aarch64/aarch64.c:
	(cortexa57_regmove_cost): New cost table for A57. 
	(cortexa53_regmove_cost): New cost table for A53.
	Increase GP2FP/FP2GP cost to spilling from integer to FP registers.

> -----Original Message-----
> From: Marcus Shawcroft [mailto:marcus.shawcroft@gmail.com]
> Sent: 04 September 2014 17:40
> To: Wilco Dijkstra
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 4/4] AArch64: Add regmove_costs for Cortex-A57 and A53
> 
> On 4 September 2014 15:47, Wilco Dijkstra <wdijkstr@arm.com> wrote:
> > This patch adds regmove_costs for Cortex-A57 and A53, and sets the cost of GP2FP/FP2GP
> higher than
> > memory cost to block the register allocator allocating integer values in FP registers.
> >
> > Overall these patches give 2-3% speedup on SPEC.
> >
> > This passes all regression tests (with this fix
> > https://gcc.gnu.org/ml/gcc-patches/2014-09/msg00356.html).
> >
> > OK for commit?
> >
> > Wilco
> >
> > ChangeLog:
> > 2014-09-04  Wilco Dijkstra  <wdijkstr@arm.com>
> >
> >         * gcc/config/aarch64/aarch64.c:
> >         Add cortexa57_regmove_cost and cortexa53_regmove_cost to avoid
> >         spilling from integer to FP registers.
> 
> Write a proper ChangeLog entry please.
> 
> Keep the GP2GP cost aligned with generic until we have justification
> to change it.
> 
> /Marcus
---
 gcc/config/aarch64/aarch64.c | 24 ++++++++++++++++++++++--
 1 file changed, 22 insertions(+), 2 deletions(-)
diff mbox

Patch

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 62b0168..bb092ca 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -218,6 +218,26 @@  static const struct cpu_regmove_cost generic_regmove_cost =
   NAMED_PARAM (FP2FP, 2)
 };
 
+static const struct cpu_regmove_cost cortexa57_regmove_cost =
+{
+  NAMED_PARAM (GP2GP, 1),
+  /* Avoid the use of slow int<->fp moves for spilling by setting
+     their cost higher than memmov_cost.  */
+  NAMED_PARAM (GP2FP, 5),
+  NAMED_PARAM (FP2GP, 5),
+  NAMED_PARAM (FP2FP, 2)
+};
+
+static const struct cpu_regmove_cost cortexa53_regmove_cost =
+{
+  NAMED_PARAM (GP2GP, 1),
+  /* Avoid the use of slow int<->fp moves for spilling by setting
+     their cost higher than memmov_cost.  */
+  NAMED_PARAM (GP2FP, 5),
+  NAMED_PARAM (FP2GP, 5),
+  NAMED_PARAM (FP2FP, 2)
+};
+
 /* Generic costs for vector insn classes.  */
 #if HAVE_DESIGNATED_INITIALIZERS && GCC_VERSION >= 2007
 __extension__
@@ -275,7 +295,7 @@  static const struct tune_params cortexa53_tunings =
 {
   &cortexa53_extra_costs,
   &generic_addrcost_table,
-  &generic_regmove_cost,
+  &cortexa53_regmove_cost,
   &generic_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
   NAMED_PARAM (issue_rate, 2)
@@ -285,7 +305,7 @@  static const struct tune_params cortexa57_tunings =
 {
   &cortexa57_extra_costs,
   &cortexa57_addrcost_table,
-  &generic_regmove_cost,
+  &cortexa57_regmove_cost,
   &cortexa57_vector_cost,
   NAMED_PARAM (memmov_cost, 4),
   NAMED_PARAM (issue_rate, 3)