| Message ID | 1410182892-18647-7-git-send-email-wens@csie.org |
|---|---|
| State | Superseded |
| Delegated to: | Ian Campbell |
| Headers | show |
On Mon, 2014-09-08 at 21:28 +0800, Chen-Yu Tsai wrote: > From: Maxime Ripard <maxime.ripard@free-electrons.com> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] > Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hi Il 08/set/2014 15:36 "Chen-Yu Tsai" <wens@csie.org> ha scritto: > > From: Maxime Ripard <maxime.ripard@free-electrons.com> > > Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> > Signed-off-by: Hans de Goede <hdegoede@redhat.com> > [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 muxing"] > Signed-off-by: Chen-Yu Tsai <wens@csie.org> > --- > arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c > index f2cedbb..fc6aa4b 100644 > --- a/arch/arm/cpu/armv7/sunxi/board.c > +++ b/arch/arm/cpu/armv7/sunxi/board.c > @@ -54,6 +54,10 @@ int gpio_init(void) > sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); > sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); > sunxi_gpio_set_pull(SUNXI_GPB(23), 1); > +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) > + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2); > + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2); > + sunxi_gpio_set_pull(SUNXI_GPH(21), 1); > #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) > sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); > sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); > -- > 2.1.0 > I don't know if it is correct that every architecture has a specific function to MUX, but can we define what is 2 2 and 1? Michael > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot
On Mon, Sep 22, 2014 at 2:10 PM, Michael Trimarchi <michael@amarulasolutions.com> wrote: > Hi > > Il 08/set/2014 15:36 "Chen-Yu Tsai" <wens@csie.org> ha scritto: > > >> >> From: Maxime Ripard <maxime.ripard@free-electrons.com> >> >> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> >> Signed-off-by: Hans de Goede <hdegoede@redhat.com> >> [wens@csie.org: commit message was "ARM: sunxi: Setup the A31 UART0 >> muxing"] >> Signed-off-by: Chen-Yu Tsai <wens@csie.org> >> --- >> arch/arm/cpu/armv7/sunxi/board.c | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/arm/cpu/armv7/sunxi/board.c >> b/arch/arm/cpu/armv7/sunxi/board.c >> index f2cedbb..fc6aa4b 100644 >> --- a/arch/arm/cpu/armv7/sunxi/board.c >> +++ b/arch/arm/cpu/armv7/sunxi/board.c >> @@ -54,6 +54,10 @@ int gpio_init(void) >> sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); >> sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); >> sunxi_gpio_set_pull(SUNXI_GPB(23), 1); >> +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) >> + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2); >> + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2); >> + sunxi_gpio_set_pull(SUNXI_GPH(21), 1); >> #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) >> sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); >> sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX); >> -- >> 2.1.0 >> > > I don't know if it is correct that every architecture has a specific > function to MUX, but can we define what is 2 2 and 1? Yes they do. I will add them in a patch before this one in v2, and also a separate patch to clean up the existing sunxi_gpio_set_pull calls. ChenYu
diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c index f2cedbb..fc6aa4b 100644 --- a/arch/arm/cpu/armv7/sunxi/board.c +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -54,6 +54,10 @@ int gpio_init(void) sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); sunxi_gpio_set_pull(SUNXI_GPB(23), 1); +#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN6I) + sunxi_gpio_set_cfgpin(SUNXI_GPH(20), 2); + sunxi_gpio_set_cfgpin(SUNXI_GPH(21), 2); + sunxi_gpio_set_pull(SUNXI_GPH(21), 1); #elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_SUN5I) sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB19_UART0_TX); sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB20_UART0_RX);