From patchwork Wed Sep 3 15:37:15 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gabriel Fernandez X-Patchwork-Id: 385558 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 39894140216 for ; Thu, 4 Sep 2014 01:40:13 +1000 (EST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1756671AbaICPjw (ORCPT ); Wed, 3 Sep 2014 11:39:52 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:42169 "EHLO mx08-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1756323AbaICPju (ORCPT ); Wed, 3 Sep 2014 11:39:50 -0400 Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-00178001.pphosted.com (8.14.5/8.14.5) with SMTP id s83FUGPE020150; Wed, 3 Sep 2014 17:37:45 +0200 Received: from beta.dmz-us.st.com (beta.dmz-us.st.com [167.4.1.35]) by mx08-00178001.pphosted.com with ESMTP id 1p5v5jujxu-1 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-SHA bits=256 verify=NOT); Wed, 03 Sep 2014 17:37:45 +0200 Received: from zeta.dmz-us.st.com (ns4.st.com [167.4.16.71]) by beta.dmz-us.st.com (STMicroelectronics) with ESMTP id 0B82F2F; Wed, 3 Sep 2014 15:37:42 +0000 (GMT) Received: from mail7.sgp.st.com (unknown [164.129.223.81]) by zeta.dmz-us.st.com (STMicroelectronics) with ESMTP id 3B88654; Wed, 3 Sep 2014 15:37:39 +0000 (GMT) Received: from lmenx315.lme.st.com ([10.201.19.41]) by mail7.sgp.st.com (MOS 4.3.3-GA) with ESMTP id BZR33674 (AUTH frq07381); Wed, 3 Sep 2014 17:37:31 +0200 From: Gabriel FERNANDEZ To: Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Srinivas Kandagatla , Maxime Coquelin , Patrice Chotard , Russell King , Kishon Vijay Abraham I , Grant Likely Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kernel@stlinux.com, Gabriel Fernandez , Giuseppe Condorelli Subject: [PATCH v2 6/8] phy: miphy28lp: Add SSC support for SATA Date: Wed, 3 Sep 2014 17:37:15 +0200 Message-Id: <1409758637-28654-7-git-send-email-gabriel.fernandez@linaro.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1409758637-28654-1-git-send-email-gabriel.fernandez@linaro.org> References: <1409758637-28654-1-git-send-email-gabriel.fernandez@linaro.org> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:5.12.52, 1.0.27, 0.0.0000 definitions=2014-09-03_07:2014-09-03, 2014-09-03, 1970-01-01 signatures=0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch to tune on/off the ssc on miphy sata setup. User can now enable ssc via dt blob, it is useful to reduce effects of EMI. Signed-off-by: Giuseppe Condorelli Signed-off-by: Gabriel Fernandez --- .../devicetree/bindings/phy/phy-miphy28lp.txt | 1 + drivers/phy/phy-miphy28lp.c | 35 ++++++++++++++++++++++ 2 files changed, 36 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt index 5e307af..49bb7bb 100644 --- a/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt +++ b/Documentation/devicetree/bindings/phy/phy-miphy28lp.txt @@ -39,6 +39,7 @@ Optional properties (port (child) node): register. - st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive line). +- st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe). example: diff --git a/drivers/phy/phy-miphy28lp.c b/drivers/phy/phy-miphy28lp.c index aa36cea..b36e737 100644 --- a/drivers/phy/phy-miphy28lp.c +++ b/drivers/phy/phy-miphy28lp.c @@ -140,6 +140,7 @@ struct miphy28lp_phy { bool osc_force_ext; bool osc_rdy; bool px_rx_pol_inv; + bool ssc; struct reset_control *miphy_rst; @@ -604,6 +605,36 @@ static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val) return miphy_osc_is_ready(miphy_phy); } +static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy) +{ + u8 val; + + /* Compensate Tx impedance to avoid out of range values */ + if (miphy_phy->ssc) { + /* + * Enable the SSC on PLL for all banks + * SSC Modulation @ 31 KHz and 4000 ppm modulation amp + */ + + val = readb_relaxed(miphy_phy->base + 0x0c); + val |= 0x04; + writeb_relaxed(val, miphy_phy->base + 0x0c); + val = readb_relaxed(miphy_phy->base + 0x0a); + val |= 0x10; + writeb_relaxed(val, miphy_phy->base + 0x0a); + + for (val = 0; val < 3; val++) { + writeb_relaxed(val, miphy_phy->base + 0x0f); + writeb_relaxed(0x3c, miphy_phy->base + 0xe4); + writeb_relaxed(0x6c, miphy_phy->base + 0xe5); + writeb_relaxed(0x81, miphy_phy->base + 0xe6); + writeb_relaxed(0x00, miphy_phy->base + 0xe3); + writeb_relaxed(0x02, miphy_phy->base + 0xe3); + writeb_relaxed(0x00, miphy_phy->base + 0xe3); + } + } +} + static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy) { struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; @@ -643,6 +674,8 @@ static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy) writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); } + miphy_sata_tune_ssc(miphy_phy); + return miphy_is_ready(miphy_phy); } @@ -872,6 +905,8 @@ static int miphy28lp_of_probe(struct device_node *np, miphy_phy->px_rx_pol_inv = of_property_read_bool(np, "st,px_rx_pol_inv"); + miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on"); + of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); if (!miphy_phy->sata_gen) miphy_phy->sata_gen = SATA_GEN1;