Message ID | 1409596459.2228712.162374913.35CEF62E@webmail.messagingengine.com |
---|---|
State | New |
Headers | show |
On 1 September 2014 19:34, David Hoover <spm@boiteauxlettres.sent.at> wrote: > Hi, > > It seems that interrupts are not disabled by CPSIE instruction. The > current code apparently ignores (daif&PSTATE_I) for Cortex-M. The patch > below is basically identical to the patch that was attached to the > following message: > > https://lists.gnu.org/archive/html/qemu-devel/2011-06/msg00513.html Thanks for the prod on this one. I've finally got round to investigating this to the point of deciding that this change is OK (though our interrupt handling on M profile is still way different from what the architecture says it should be). I've applied this to target-arm.next, with an improved commit message: cpu-exec.c: Allow disabling of IRQs on ARM Cortex-M CPUs Correct an error in the logic for deciding whether we can take an IRQ interrupt which meant that on M profile cores it was never possible to disable them. The design here is still bogus in that M profile doesn't have separate "IRQ" and "FIQ", which are an A/R profile concept; we should ideally implement the proper priority based scheme. Signed-off-by: David Hoover <spm@boiteauxlettres.sent.at> [PMM: Wrote a proper commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org> -- PMM
diff --git a/cpu-exec.c b/cpu-exec.c index c6aad74..fdebe2b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -610,8 +610,8 @@ int cpu_exec(CPUArchState *env) We avoid this by disabling interrupts when pc contains a magic address. */ if (interrupt_request & CPU_INTERRUPT_HARD - && ((IS_M(env) && env->regs[15] < 0xfffffff0) - || !(env->daif & PSTATE_I))) { + && !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { cpu->exception_index = EXCP_IRQ; cc->do_interrupt(cpu);