From patchwork Mon Sep 1 14:38:16 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Tocar X-Patchwork-Id: 384886 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id CDEA414012B for ; Tue, 2 Sep 2014 00:38:56 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; q=dns; s=default; b=HDV8AAkVNMdJxJTjK kLMYAGzh+wkukV7GGks7hc1PPkaYp+YdRpJRNIYQyTdN0kv+7xf+Qx9ZdArPvRgn gLxn1gUFEgVhwCzp/QmdLz2uMdT8JQATwQVvfnDhjjp1HgR/aRSUgLrzZUOnFxOu eamWp9whXg+qduXljRCqsbFgjI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:references:mime-version :content-type:in-reply-to; s=default; bh=DjCCCw2eQ+/lJ3jgxnzuV+f dVxg=; b=hfTZwev8o9nqzsb981D2N1b4Wh8hWhfFXoZ7olzTzTO/98HuolEswBs WsSvMtakN1zwOc/v1mHmoRcdz/TQa5IbAG0dlpDQokQQqu4Lx9/RW4Ry0AlRdyNk B3imV14/66gDf/7z6sqa8MgEaCWO1XLSFmCqiH4jzMuHVc/vDWRs= Received: (qmail 22255 invoked by alias); 1 Sep 2014 14:38:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 22230 invoked by uid 89); 1 Sep 2014 14:38:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-yh0-f45.google.com Received: from mail-yh0-f45.google.com (HELO mail-yh0-f45.google.com) (209.85.213.45) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Mon, 01 Sep 2014 14:38:28 +0000 Received: by mail-yh0-f45.google.com with SMTP id i57so3442712yha.18 for ; Mon, 01 Sep 2014 07:38:25 -0700 (PDT) X-Received: by 10.236.53.69 with SMTP id f45mr43290912yhc.53.1409582305488; Mon, 01 Sep 2014 07:38:25 -0700 (PDT) Received: from msticlxl7.ims.intel.com (jfdmzpr03-ext.jf.intel.com. [134.134.139.72]) by mx.google.com with ESMTPSA id n6sm4185280yho.32.2014.09.01.07.38.23 for (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 01 Sep 2014 07:38:24 -0700 (PDT) Date: Mon, 1 Sep 2014 18:38:16 +0400 From: Ilya Tocar To: Jakub Jelinek Cc: GCC Patches Subject: Re: [PATCH] PR62120 Message-ID: <20140901143816.GC26266@msticlxl7.ims.intel.com> References: <20140901104314.GB26266@msticlxl7.ims.intel.com> <20140901105552.GN17454@tucnak.redhat.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20140901105552.GN17454@tucnak.redhat.com> User-Agent: Mutt/1.5.23 (2014-03-12) X-IsSubscribed: yes > Please mention the PR in the ChangeLog entry and add some testcases > (can be gcc.target/i386/, but we should have it tested). > Does this change anything on say register short sil __asm ("sil"); in 32-bit > mode (when it IMHO should be rejected too?)? > Do we support "sil" at all? In i386.h i see: /* Note we are omitting these since currently I don't know how to get gcc to use these, since they want the same but different number as al, and ax. */ #define QI_REGISTER_NAMES \ {"al", "dl", "cl", "bl", "sil", "dil", "bpl", "spl",} And gcc doesn't recognize sil. Added testcase, and fixed avx512f-additional-reg-names.c to be valid on 32 bits. Ok for trunk? gcc/ 2014-09-01 Ilya Tocar PR middle-end/62120 * varasm.c (decode_reg_name_and_count): Check availability for registers from ADDITIONAL_REGISTER_NAMES. Testsuite/ 2014-09-01 Ilya Tocar PR middle-end/62120 * gcc.target/i386/avx512f-additional-reg-names.c: Use register vaild in 32-bit mode. * gcc.target/i386/pr62120.c: New. --- gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c | 2 +- gcc/testsuite/gcc.target/i386/pr62120.c | 7 +++++++ gcc/varasm.c | 5 +++-- 3 files changed, 11 insertions(+), 3 deletions(-) create mode 100644 gcc/testsuite/gcc.target/i386/pr62120.c diff --git a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c index 164a1de..98a9052 100644 --- a/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c +++ b/gcc/testsuite/gcc.target/i386/avx512f-additional-reg-names.c @@ -3,7 +3,7 @@ void foo () { - register int zmm_var asm ("zmm9") __attribute__((unused)); + register int zmm_var asm ("zmm7") __attribute__((unused)); __asm__ __volatile__("vxorpd %%zmm0, %%zmm0, %%zmm7\n" : : : "zmm7" ); } diff --git a/gcc/testsuite/gcc.target/i386/pr62120.c b/gcc/testsuite/gcc.target/i386/pr62120.c new file mode 100644 index 0000000..8870d48 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr62120.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options "-mno-sse" } */ + +void foo () +{ + register int zmm_var asm ("ymm9");/* { dg-error "invalid register name" } */ +} diff --git a/gcc/varasm.c b/gcc/varasm.c index de4479c..9638665 100644 --- a/gcc/varasm.c +++ b/gcc/varasm.c @@ -888,7 +888,7 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs) if (asmspec[0] != 0 && i < 0) { i = atoi (asmspec); - if (i < FIRST_PSEUDO_REGISTER && i >= 0) + if (i < FIRST_PSEUDO_REGISTER && i >= 0 && reg_names[i][0]) return i; else return -2; @@ -925,7 +925,8 @@ decode_reg_name_and_count (const char *asmspec, int *pnregs) for (i = 0; i < (int) ARRAY_SIZE (table); i++) if (table[i].name[0] - && ! strcmp (asmspec, table[i].name)) + && ! strcmp (asmspec, table[i].name) + && reg_names[table[i].number][0]) return table[i].number; } #endif /* ADDITIONAL_REGISTER_NAMES */