AHCI: disable sntf cap for ich8

Submitted by Shaohua Li on Nov. 16, 2009, 1:56 a.m.

Details

Message ID 20091116015605.GA21717@sli10-desk.sh.intel.com
State Not Applicable
Delegated to: David Miller
Headers show

Commit Message

Shaohua Li Nov. 16, 2009, 1:56 a.m.
I obseved there is a sata_async_notification() for every ahci interrupt. But the
async notification does nothing (this is hard disk drive and no pmp). This cause
cpu wastes some time on sntf register access.

It appears ICH AHCI doesn't support SNotification register, but the controller
reports it does. After quirking it, the async notification disappears.

PS. it appears all ICH don't support SNotification register from ICH manual, don't
know if we need quirk all ICH. I don't have machines with all kinds of ICH.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
---
 drivers/ata/ahci.c |   20 ++++++++++++++++++--
 1 file changed, 18 insertions(+), 2 deletions(-)

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Comments

Jeff Garzik Nov. 17, 2009, 3:19 a.m.
On 11/15/2009 08:56 PM, Shaohua Li wrote:
> I obseved there is a sata_async_notification() for every ahci interrupt. But the
> async notification does nothing (this is hard disk drive and no pmp). This cause
> cpu wastes some time on sntf register access.
>
> It appears ICH AHCI doesn't support SNotification register, but the controller
> reports it does. After quirking it, the async notification disappears.

Patch applied.


> PS. it appears all ICH don't support SNotification register from ICH manual, don't
> know if we need quirk all ICH. I don't have machines with all kinds of ICH.

You work for Intel -- you or somebody needs to research and figure this 
out...  This is an Intel vendor issue that only Intel can definitively 
resolve.

	Jeff


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Patch hide | download patch | download mbox

Index: linux/drivers/ata/ahci.c
===================================================================
--- linux.orig/drivers/ata/ahci.c	2009-11-16 09:36:40.000000000 +0800
+++ linux/drivers/ata/ahci.c	2009-11-16 09:53:44.000000000 +0800
@@ -113,6 +113,7 @@  enum {
 	board_ahci_mcp65	= 6,
 	board_ahci_nopmp	= 7,
 	board_ahci_yesncq	= 8,
+	board_ahci_nosntf	= 9,
 
 	/* global controller registers */
 	HOST_CAP		= 0x00, /* host capabilities */
@@ -235,6 +236,7 @@  enum {
 	AHCI_HFLAG_NO_SUSPEND		= (1 << 10), /* don't suspend */
 	AHCI_HFLAG_SRST_TOUT_IS_OFFLINE	= (1 << 11), /* treat SRST timeout as
 							link offline */
+	AHCI_HFLAG_NO_SNTF		= (1 << 12), /* no sntf */
 
 	/* ap->flags bits */
 
@@ -508,7 +510,7 @@  static const struct ata_port_info ahci_p
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
-	/* board_ahci_yesncq */
+	[board_ahci_yesncq] =
 	{
 		AHCI_HFLAGS	(AHCI_HFLAG_YES_NCQ),
 		.flags		= AHCI_FLAG_COMMON,
@@ -516,6 +518,14 @@  static const struct ata_port_info ahci_p
 		.udma_mask	= ATA_UDMA6,
 		.port_ops	= &ahci_ops,
 	},
+	[board_ahci_nosntf] =
+	{
+		AHCI_HFLAGS	(AHCI_HFLAG_NO_SNTF),
+		.flags		= AHCI_FLAG_COMMON,
+		.pio_mask	= ATA_PIO4,
+		.udma_mask	= ATA_UDMA6,
+		.port_ops	= &ahci_ops,
+	},
 };
 
 static const struct pci_device_id ahci_pci_tbl[] = {
@@ -531,7 +541,7 @@  static const struct pci_device_id ahci_p
 	{ PCI_VDEVICE(INTEL, 0x2683), board_ahci }, /* ESB2 */
 	{ PCI_VDEVICE(INTEL, 0x27c6), board_ahci }, /* ICH7-M DH */
 	{ PCI_VDEVICE(INTEL, 0x2821), board_ahci }, /* ICH8 */
-	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci }, /* ICH8 */
+	{ PCI_VDEVICE(INTEL, 0x2822), board_ahci_nosntf }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2824), board_ahci }, /* ICH8 */
 	{ PCI_VDEVICE(INTEL, 0x2829), board_ahci }, /* ICH8M */
 	{ PCI_VDEVICE(INTEL, 0x282a), board_ahci }, /* ICH8M */
@@ -849,6 +859,12 @@  static void ahci_save_initial_config(str
 		cap &= ~HOST_CAP_PMP;
 	}
 
+	if ((cap & HOST_CAP_SNTF) && (hpriv->flags & AHCI_HFLAG_NO_SNTF)) {
+		dev_printk(KERN_INFO, &pdev->dev,
+			   "controller can't do SNTF, turning off CAP_SNTF\n");
+		cap &= ~HOST_CAP_SNTF;
+	}
+
 	if (pdev->vendor == PCI_VENDOR_ID_JMICRON && pdev->device == 0x2361 &&
 	    port_map != 1) {
 		dev_printk(KERN_INFO, &pdev->dev,