Patchwork [i386,AVX512,33/n] Add patterns for compress, expand.

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Submitter Kirill Yukhin
Date Aug. 29, 2014, 2 p.m.
Message ID <20140829140053.GE18938@msticlxl57.ims.intel.com>
Download mbox | patch
Permalink /patch/384253/
State New
Headers show

Comments

Kirill Yukhin - Aug. 29, 2014, 2 p.m.
Hello,
Patch in the bottom extends support of compress and expand
insns.

Bootstrapped.
AVX-512* tests on top of patch-set all pass
under simulator.

Is it ok for trunk?

gcc/
	* config/i386/sse.md
	(define_mode_iterator VI48F): New.
	(define_insn "avx512f_compress<mode>_mask"): Delete.
	(define_insn "<avx512>_compress<mode>_mask"): New.
	(define_insn "avx512f_compressstore<mode>_mask"): Delete.
	(define_insn "<avx512>_compressstore<mode>_mask"): New.
	(define_expand "avx512f_expand<mode>_maskz"): Delete.
	(define_expand "<avx512>_expand<mode>_maskz"): New.
	(define_insn "avx512f_expand<mode>_mask"): Delete.
	(define_insn "<avx512>_expand<mode>_mask"): New.

--
Thanks, K
Uros Bizjak - Aug. 30, 2014, 8:37 a.m.
On Fri, Aug 29, 2014 at 4:00 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:

> Patch in the bottom extends support of compress and expand
> insns.
>
> Bootstrapped.
> AVX-512* tests on top of patch-set all pass
> under simulator.
>
> Is it ok for trunk?
>
> gcc/
>         * config/i386/sse.md
>         (define_mode_iterator VI48F): New.
>         (define_insn "avx512f_compress<mode>_mask"): Delete.
>         (define_insn "<avx512>_compress<mode>_mask"): New.
>         (define_insn "avx512f_compressstore<mode>_mask"): Delete.
>         (define_insn "<avx512>_compressstore<mode>_mask"): New.
>         (define_expand "avx512f_expand<mode>_maskz"): Delete.
>         (define_expand "<avx512>_expand<mode>_maskz"): New.
>         (define_insn "avx512f_expand<mode>_mask"): Delete.
>         (define_insn "<avx512>_expand<mode>_mask"): New.

Again, rename instead of delete/new.

The patch is OK.

Please note that you can use UNSPEC_COMPRESS everywhere, there is no
need for UNSPEC_COMPRESS_STORE and can be deleted. On a related note,
it looks to me that UNSPEC_COMPRESS patterns can be merged together by
using nonimmediate operand 0 and matched memory. Please see the last
constraint of sse_movhlps for example. This can be a follow-up patch.

Thanks,
Uros.
Kirill Yukhin - Sept. 9, 2014, 11:36 a.m.
Hello UroŇ°,
On 30 Aug 10:37, Uros Bizjak wrote:
> On Fri, Aug 29, 2014 at 4:00 PM, Kirill Yukhin <kirill.yukhin@gmail.com> wrote:
> Please note that you can use UNSPEC_COMPRESS everywhere, there is no
> need for UNSPEC_COMPRESS_STORE and can be deleted. On a related note,
> it looks to me that UNSPEC_COMPRESS patterns can be merged together by
> using nonimmediate operand 0 and matched memory. Please see the last
> constraint of sse_movhlps for example. This can be a follow-up patch.
Thanks, we'll look at this later.

--
Thanks, K

Patch

diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md
index c505526..70fe390 100644
--- a/gcc/config/i386/sse.md
+++ b/gcc/config/i386/sse.md
@@ -519,6 +519,12 @@ 
   (V16SI "TARGET_AVX512F") (V16SF "TARGET_AVX512F")
   (V8DI  "TARGET_AVX512F") (V8DF  "TARGET_AVX512F")])
 (define_mode_iterator VI48F_512 [V16SI V16SF V8DI V8DF])
+(define_mode_iterator VI48F
+  [V16SI V16SF V8DI V8DF
+   (V8SI "TARGET_AVX512VL") (V8SF "TARGET_AVX512VL")
+   (V4DI "TARGET_AVX512VL") (V4DF "TARGET_AVX512VL")
+   (V4SI "TARGET_AVX512VL") (V4SF "TARGET_AVX512VL")
+   (V2DI "TARGET_AVX512VL") (V2DF "TARGET_AVX512VL")])
 
 ;; Mapping from float mode to required SSE level
 (define_mode_attr sse
@@ -16744,11 +16750,11 @@ 
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "avx512f_compress<mode>_mask"
-  [(set (match_operand:VI48F_512 0 "register_operand" "=v")
-	(unspec:VI48F_512
-	  [(match_operand:VI48F_512 1 "register_operand" "v")
-	   (match_operand:VI48F_512 2 "vector_move_operand" "0C")
+(define_insn "<avx512>_compress<mode>_mask"
+  [(set (match_operand:VI48F 0 "register_operand" "=v")
+	(unspec:VI48F
+	  [(match_operand:VI48F 1 "register_operand" "v")
+	   (match_operand:VI48F 2 "vector_move_operand" "0C")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk")]
 	  UNSPEC_COMPRESS))]
   "TARGET_AVX512F"
@@ -16757,10 +16763,10 @@ 
    (set_attr "prefix" "evex")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_insn "avx512f_compressstore<mode>_mask"
-  [(set (match_operand:VI48F_512 0 "memory_operand" "=m")
-	(unspec:VI48F_512
-	  [(match_operand:VI48F_512 1 "register_operand" "x")
+(define_insn "<avx512>_compressstore<mode>_mask"
+  [(set (match_operand:VI48F 0 "memory_operand" "=m")
+	(unspec:VI48F
+	  [(match_operand:VI48F 1 "register_operand" "x")
 	   (match_dup 0)
 	   (match_operand:<avx512fmaskmode> 2 "register_operand" "Yk")]
 	  UNSPEC_COMPRESS_STORE))]
@@ -16771,21 +16777,21 @@ 
    (set_attr "memory" "store")
    (set_attr "mode" "<sseinsnmode>")])
 
-(define_expand "avx512f_expand<mode>_maskz"
-  [(set (match_operand:VI48F_512 0 "register_operand")
-	(unspec:VI48F_512
-	  [(match_operand:VI48F_512 1 "nonimmediate_operand")
-	   (match_operand:VI48F_512 2 "vector_move_operand")
+(define_expand "<avx512>_expand<mode>_maskz"
+  [(set (match_operand:VI48F 0 "register_operand")
+	(unspec:VI48F
+	  [(match_operand:VI48F 1 "nonimmediate_operand")
+	   (match_operand:VI48F 2 "vector_move_operand")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand")]
 	  UNSPEC_EXPAND))]
   "TARGET_AVX512F"
   "operands[2] = CONST0_RTX (<MODE>mode);")
 
-(define_insn "avx512f_expand<mode>_mask"
-  [(set (match_operand:VI48F_512 0 "register_operand" "=v,v")
-	(unspec:VI48F_512
-	  [(match_operand:VI48F_512 1 "nonimmediate_operand" "v,m")
-	   (match_operand:VI48F_512 2 "vector_move_operand" "0C,0C")
+(define_insn "<avx512>_expand<mode>_mask"
+  [(set (match_operand:VI48F 0 "register_operand" "=v,v")
+	(unspec:VI48F
+	  [(match_operand:VI48F 1 "nonimmediate_operand" "v,m")
+	   (match_operand:VI48F 2 "vector_move_operand" "0C,0C")
 	   (match_operand:<avx512fmaskmode> 3 "register_operand" "Yk,Yk")]
 	  UNSPEC_EXPAND))]
   "TARGET_AVX512F"