From patchwork Fri Aug 29 13:23:25 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 384228 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id A250414010B for ; Fri, 29 Aug 2014 23:24:00 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=Tiepg6g6hv2l6pgKuqCsupCkt9gaJ7T9/JmCZfKg0Q4gHj2gos r3v61LnbCfTOINwIotd4+PAEfmubte40PbzfBEREEf/bfp61pn6CsKvt555mQQQZ YJ01krVwFN4SAp2h0A8gpeq2Kg6YeN8SM+LcC0YNg4LNr9xDukjPqWkyc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=AudK0p+6llw98dBnxI+XexSmKd4=; b=CsREOM48MN/Kp2XyzuOu flN3STscYvZr3jR92IH2kZSJ+3Tr4ZfuiGtrljrG3wT0UeBsfXOQK0o+kVp3nPdr irZTG+DBXbuOHACeUTOqqOzKDO882VwZT41rY1HaKFRtfCsQuRHar14v76j6Zsob HGWafM+WSWMwyBiOOl0ZyU0= Received: (qmail 417 invoked by alias); 29 Aug 2014 13:23:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 408 invoked by uid 89); 29 Aug 2014 13:23:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.0 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wi0-f181.google.com Received: from mail-wi0-f181.google.com (HELO mail-wi0-f181.google.com) (209.85.212.181) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Fri, 29 Aug 2014 13:23:44 +0000 Received: by mail-wi0-f181.google.com with SMTP id e4so2506337wiv.8 for ; Fri, 29 Aug 2014 06:23:40 -0700 (PDT) X-Received: by 10.180.183.36 with SMTP id ej4mr3690546wic.77.1409318620873; Fri, 29 Aug 2014 06:23:40 -0700 (PDT) Received: from msticlxl57.ims.intel.com ([192.55.54.40]) by mx.google.com with ESMTPSA id au4sm18615686wjc.15.2014.08.29.06.23.37 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 29 Aug 2014 06:23:40 -0700 (PDT) Date: Fri, 29 Aug 2014 17:23:25 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches , kirill.yukhin@gmail.com Subject: [PATCH i386 AVX512] [31/n] Update float unspec namely storeu, rcp14, rsqrt14, scalef, getexp, fixupimm, rndscale, getmant. Message-ID: <20140829132324.GC18938@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, Patch in the bottom updates few UNSPEC insn patterns w/ new mode iterator. Additionally names were slightly changed. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ * config/i386/i386.c (avx512f_getmantv2df_round): Rename to ... (avx512f_vgetmantv2df_round): this. (avx512f_getmantv4sf_round): Rename to ... (avx512f_vgetmantv4sf_round): this. (ix86_expand_args_builtin): Handle avx512vl_getmantv8sf_mask, avx512vl_getmantv4df_mask, avx512vl_getmantv4sf_mask, avx512vl_getmantv2df_mask. (ix86_expand_round_builtin): Handle avx512f_vgetmantv2df_round, avx512f_vgetmantv4sf_round. * config/i386/sse.md (define_insn "avx512f_storeu512_mask"): Delete. (define_insn "_storeu_mask"): New. (define_insn "rcp14"): Use VF_AVX512VL. (define_insn "rsqrt14"): Ditto. (define_insn "avx512f_scalef"): Delete. (define_insn "_scalef"): New. (define_insn "avx512f_getexp"): Delete. (define_insn "_getexp"): New. (define_expand "avx512f_fixupimm_maskz"): Delete. (define_expand "_fixupimm_maskz"): New. (define_insn "avx512f_fixupimm"): Delete. (define_insn "_fixupimm"): New. (define_insn "avx512f_fixupimm_mask"): Delete. (define_insn "_fixupimm_mask"): New. (define_insn "avx512f_rndscale"): Delete. (define_insn "_rndscale"): New. (define_insn "avx512f_getmant"): Delete. (define_insn "_getmant"): New. (define_insn "avx512f_getmant"): Rename to ... (define_insn "avx512f_vgetmant"): this. --- Thanks, K diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 61b33782..ff37ffe 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -30317,8 +30317,8 @@ static const struct builtin_description bdesc_round_args[] = { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_sgetexpv4sf_round, "__builtin_ia32_getexpss128_round", IX86_BUILTIN_GETEXPSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv8df_mask_round, "__builtin_ia32_getmantpd512_mask", IX86_BUILTIN_GETMANTPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_INT_V8DF_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv16sf_mask_round, "__builtin_ia32_getmantps512_mask", IX86_BUILTIN_GETMANTPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_INT_V16SF_HI_INT }, - { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT }, - { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_getmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv2df_round, "__builtin_ia32_getmantsd_round", IX86_BUILTIN_GETMANTSD128, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT_INT }, + { OPTION_MASK_ISA_AVX512F, CODE_FOR_avx512f_vgetmantv4sf_round, "__builtin_ia32_getmantss_round", IX86_BUILTIN_GETMANTSS128, UNKNOWN, (int) V4SF_FTYPE_V4SF_V4SF_INT_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv8df3_mask_round, "__builtin_ia32_maxpd512_mask", IX86_BUILTIN_MAXPD512, UNKNOWN, (int) V8DF_FTYPE_V8DF_V8DF_V8DF_QI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_smaxv16sf3_mask_round, "__builtin_ia32_maxps512_mask", IX86_BUILTIN_MAXPS512, UNKNOWN, (int) V16SF_FTYPE_V16SF_V16SF_V16SF_HI_INT }, { OPTION_MASK_ISA_AVX512F, CODE_FOR_sse2_vmsmaxv2df3_round, "__builtin_ia32_maxsd_round", IX86_BUILTIN_MAXSD_ROUND, UNKNOWN, (int) V2DF_FTYPE_V2DF_V2DF_INT }, @@ -34110,6 +34110,10 @@ ix86_expand_args_builtin (const struct builtin_description *d, case CODE_FOR_avx_vpermilv4df: case CODE_FOR_avx512f_getmantv8df_mask: case CODE_FOR_avx512f_getmantv16sf_mask: + case CODE_FOR_avx512vl_getmantv8sf_mask: + case CODE_FOR_avx512vl_getmantv4df_mask: + case CODE_FOR_avx512vl_getmantv4sf_mask: + case CODE_FOR_avx512vl_getmantv2df_mask: error ("the last argument must be a 4-bit immediate"); return const0_rtx; @@ -34516,8 +34520,8 @@ ix86_expand_round_builtin (const struct builtin_description *d, { case CODE_FOR_avx512f_getmantv8df_mask_round: case CODE_FOR_avx512f_getmantv16sf_mask_round: - case CODE_FOR_avx512f_getmantv2df_round: - case CODE_FOR_avx512f_getmantv4sf_round: + case CODE_FOR_avx512f_vgetmantv2df_round: + case CODE_FOR_avx512f_vgetmantv4sf_round: error ("the immediate argument must be a 4-bit immediate"); return const0_rtx; case CODE_FOR_avx512f_cmpv8df3_mask_round: diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index b9aa581..d85f9a4 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -1170,11 +1170,11 @@ ] (const_string "")))]) -(define_insn "avx512f_storeu512_mask" - [(set (match_operand:VF_512 0 "memory_operand" "=m") - (vec_merge:VF_512 - (unspec:VF_512 - [(match_operand:VF_512 1 "register_operand" "v")] +(define_insn "_storeu_mask" + [(set (match_operand:VF_AVX512VL 0 "memory_operand" "=m") + (vec_merge:VF_AVX512VL + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "register_operand" "v")] UNSPEC_STOREU) (match_dup 0) (match_operand: 2 "register_operand" "Yk")))] @@ -1183,6 +1183,8 @@ switch (get_attr_mode (insn)) { case MODE_V16SF: + case MODE_V8SF: + case MODE_V4SF: return "vmovups\t{%1, %0%{%2%}|%0%{%2%}, %1}"; default: return "vmovu\t{%1, %0%{%2%}|%0%{%2%}, %1}"; @@ -1702,9 +1704,9 @@ (set_attr "mode" "SF")]) (define_insn "rcp14" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "vm")] UNSPEC_RCP14))] "TARGET_AVX512F" "vrcp14\t{%1, %0|%0, %1}" @@ -1797,9 +1799,9 @@ (set_attr "mode" "")]) (define_insn "rsqrt14" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 - [(match_operand:VF_512 1 "nonimmediate_operand" "vm")] + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "vm")] UNSPEC_RSQRT14))] "TARGET_AVX512F" "vrsqrt14\t{%1, %0|%0, %1}" @@ -7110,11 +7112,11 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_scalef" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 - [(match_operand:VF_512 1 "register_operand" "v") - (match_operand:VF_512 2 "" "")] +(define_insn "_scalef" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "register_operand" "v") + (match_operand:VF_AVX512VL 2 "nonimmediate_operand" "")] UNSPEC_SCALEF))] "TARGET_AVX512F" "vscalef\t{%2, %1, %0|%0, %1, %2}" @@ -7167,9 +7169,9 @@ (set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_getexp" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 [(match_operand:VF_512 1 "" "")] +(define_insn "_getexp" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL [(match_operand:VF_AVX512VL 1 "" "")] UNSPEC_GETEXP))] "TARGET_AVX512F" "vgetexp\t{%1, %0|%0, %1}"; @@ -7233,28 +7235,28 @@ }) -(define_expand "avx512f_fixupimm_maskz" - [(match_operand:VF_512 0 "register_operand") - (match_operand:VF_512 1 "register_operand") - (match_operand:VF_512 2 "register_operand") +(define_expand "_fixupimm_maskz" + [(match_operand:VF_AVX512VL 0 "register_operand") + (match_operand:VF_AVX512VL 1 "register_operand") + (match_operand:VF_AVX512VL 2 "register_operand") (match_operand: 3 "") (match_operand:SI 4 "const_0_to_255_operand") (match_operand: 5 "register_operand")] "TARGET_AVX512F" { - emit_insn (gen_avx512f_fixupimm_maskz_1 ( + emit_insn (gen__fixupimm_maskz_1 ( operands[0], operands[1], operands[2], operands[3], operands[4], CONST0_RTX (mode), operands[5] )); DONE; }) -(define_insn "avx512f_fixupimm" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 - [(match_operand:VF_512 1 "register_operand" "0") - (match_operand:VF_512 2 "register_operand" "v") - (match_operand: 3 "" "") +(define_insn "_fixupimm" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "register_operand" "0") + (match_operand:VF_AVX512VL 2 "register_operand" "v") + (match_operand: 3 "nonimmediate_operand" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM))] "TARGET_AVX512F" @@ -7262,13 +7264,13 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_fixupimm_mask" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (vec_merge:VF_512 - (unspec:VF_512 - [(match_operand:VF_512 1 "register_operand" "0") - (match_operand:VF_512 2 "register_operand" "v") - (match_operand: 3 "" "") +(define_insn "_fixupimm_mask" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (vec_merge:VF_AVX512VL + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "register_operand" "0") + (match_operand:VF_AVX512VL 2 "register_operand" "v") + (match_operand: 3 "nonimmediate_operand" "") (match_operand:SI 4 "const_0_to_255_operand")] UNSPEC_FIXUPIMM) (match_dup 1) @@ -7329,10 +7331,10 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_rndscale" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 - [(match_operand:VF_512 1 "" "") +(define_insn "_rndscale" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "") (match_operand:SI 2 "const_0_to_255_operand")] UNSPEC_ROUND))] "TARGET_AVX512F" @@ -16758,10 +16760,10 @@ (set_attr "memory" "none,load") (set_attr "mode" "")]) -(define_insn "avx512f_getmant" - [(set (match_operand:VF_512 0 "register_operand" "=v") - (unspec:VF_512 - [(match_operand:VF_512 1 "" "") +(define_insn "_getmant" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "") (match_operand:SI 2 "const_0_to_15_operand")] UNSPEC_GETMANT))] "TARGET_AVX512F" @@ -16769,7 +16771,7 @@ [(set_attr "prefix" "evex") (set_attr "mode" "")]) -(define_insn "avx512f_getmant" +(define_insn "avx512f_vgetmant" [(set (match_operand:VF_128 0 "register_operand" "=v") (vec_merge:VF_128 (unspec:VF_128