Patchwork [1/3] eLBC NAND: increase bus timeout to maximum

login
register
mail settings
Submitter Scott Wood
Date Nov. 13, 2009, 8:12 p.m.
Message ID <20091113201216.GA8313@loki.buserror.net>
Download mbox | patch
Permalink /patch/38389/
State New
Headers show

Comments

Scott Wood - Nov. 13, 2009, 8:12 p.m.
When a NAND operation is in progress, all other localbus operations
(including NOR flash) will have to wait for access to the bus.  However, the
NAND operation may take longer to complete than the default timeout.  Thus,
if NOR is accessed while a NAND operation is in progress, the NAND operation
will fail.

Signed-off-by: Scott Wood <scottwood@freescale.com>
---
 drivers/mtd/nand/fsl_elbc_nand.c |    7 +++++++
 1 files changed, 7 insertions(+), 0 deletions(-)
Artem Bityutskiy - Nov. 23, 2009, 2:36 p.m.
On Fri, 2009-11-13 at 14:12 -0600, Scott Wood wrote:
> When a NAND operation is in progress, all other localbus operations
> (including NOR flash) will have to wait for access to the bus.  However, the
> NAND operation may take longer to complete than the default timeout.  Thus,
> if NOR is accessed while a NAND operation is in progress, the NAND operation
> will fail.
> 
> Signed-off-by: Scott Wood <scottwood@freescale.com>

Taken the patches to my l2-mtd-2.6 tree.

Patch

diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index ddd37d2..58db278 100644
--- a/drivers/mtd/nand/fsl_elbc_nand.c
+++ b/drivers/mtd/nand/fsl_elbc_nand.c
@@ -946,6 +946,13 @@  static int __devinit fsl_elbc_ctrl_init(struct fsl_elbc_ctrl *ctrl)
 {
 	struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
 
+	/*
+	 * NAND transactions can tie up the bus for a long time, so set the
+	 * bus timeout to max by clearing LBCR[BMT] (highest base counter
+	 * value) and setting LBCR[BMTPS] to the highest prescaler value.
+	 */
+	clrsetbits_be32(&lbc->lbcr, LBCR_BMT, 15);
+
 	/* clear event registers */
 	setbits32(&lbc->ltesr, LTESR_NAND_MASK);
 	out_be32(&lbc->lteatr, 0);