From patchwork Wed Aug 27 13:28:55 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kirill Yukhin X-Patchwork-Id: 383457 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 5B6291400D2 for ; Wed, 27 Aug 2014 23:29:26 +1000 (EST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; q=dns; s=default; b=RzdG0CypeGPIdD7JoOKCW9dk81fxXSaYwFTxvoDiToSpwVTGKB acK0UQGRv2JhuIKkAblZcGDjk19jz3x3VUTZl9x6Yo7OFxLrQE6aay2pjrj6olSS sPV2ZtBhWhs/oNWfoMoUp0D1/be5l+nJ4ZmwoFzHLhXVNAdW++h16D7Uk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:cc:subject:message-id:mime-version:content-type; s= default; bh=2e973A8lJrSdCTtA4Sn4X04hlUw=; b=hF5e1fEWjrx1owFu28+P eU6bL+PrqK+XPokGk9QMrSlFUohRAIqW/bFPDNW54XQzeTcGcj4gNngm5KZnkhId xeTt/z5EED2AO2/bE9UmaFn9WHAqF6P/biVauH7bak23XeApQQJJDeaQKDfaFUXI UxtTafdFz1eWmYhKgHUa0o8= Received: (qmail 13810 invoked by alias); 27 Aug 2014 13:29:12 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 13791 invoked by uid 89); 27 Aug 2014 13:29:11 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-2.6 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.2 X-HELO: mail-wg0-f43.google.com Received: from mail-wg0-f43.google.com (HELO mail-wg0-f43.google.com) (74.125.82.43) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with (AES128-SHA encrypted) ESMTPS; Wed, 27 Aug 2014 13:29:10 +0000 Received: by mail-wg0-f43.google.com with SMTP id l18so209152wgh.14 for ; Wed, 27 Aug 2014 06:29:06 -0700 (PDT) X-Received: by 10.194.172.137 with SMTP id bc9mr37832082wjc.72.1409146145882; Wed, 27 Aug 2014 06:29:05 -0700 (PDT) Received: from msticlxl57.ims.intel.com (jfdmzpr02-ext.jf.intel.com. [134.134.137.71]) by mx.google.com with ESMTPSA id lv7sm3003651wic.16.2014.08.27.06.29.02 for (version=TLSv1 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 27 Aug 2014 06:29:05 -0700 (PDT) Date: Wed, 27 Aug 2014 17:28:55 +0400 From: Kirill Yukhin To: Uros Bizjak Cc: Jakub Jelinek , Richard Henderson , GCC Patches , kirill.yukhin@gmail.com Subject: [PATCH i386 AVX512] [27/n] Add byte/word plus/minus/avg. Message-ID: <20140827132854.GE7762@msticlxl57.ims.intel.com> MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) X-IsSubscribed: yes Hello, Patch extends `plusminus' and `avg' insn patterns toward AVX-512BW,VL support. Bootstrapped. AVX-512* tests on top of patch-set all pass under simulator. Is it ok for trunk? gcc/ (define_mode_iterator VI12_AVX2): Add V64QI and V32HI modes. (define_expand "_3"): Add masking. (define_insn "*_3"): Ditto. (define_expand "_uavg3"): Ditto. (define_insn "*_uavg3"): Ditto. (define_insn "*mul3"): Add EVEX version. --- Thanks, K diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 03512a5..c602eeb 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -338,8 +338,8 @@ [(V2TI "TARGET_AVX2") TI]) (define_mode_iterator VI12_AVX2 - [(V32QI "TARGET_AVX2") V16QI - (V16HI "TARGET_AVX2") V8HI]) + [(V64QI "TARGET_AVX512BW") (V32QI "TARGET_AVX2") V16QI + (V32HI "TARGET_AVX512BW") (V16HI "TARGET_AVX2") V8HI]) (define_mode_iterator VI24_AVX2 [(V16HI "TARGET_AVX2") V8HI @@ -8109,27 +8109,28 @@ (set_attr "prefix" "") (set_attr "mode" "")]) -(define_expand "_3" +(define_expand "_3" [(set (match_operand:VI12_AVX2 0 "register_operand") (sat_plusminus:VI12_AVX2 (match_operand:VI12_AVX2 1 "nonimmediate_operand") (match_operand:VI12_AVX2 2 "nonimmediate_operand")))] - "TARGET_SSE2" + "TARGET_SSE2 && && " "ix86_fixup_binary_operands_no_copy (, mode, operands);") -(define_insn "*_3" +(define_insn "*_3" [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") (sat_plusminus:VI12_AVX2 (match_operand:VI12_AVX2 1 "nonimmediate_operand" "0,v") (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm")))] - "TARGET_SSE2 && ix86_binary_operator_ok (, mode, operands)" + "TARGET_SSE2 && && + && ix86_binary_operator_ok (, mode, operands)" "@ p\t{%2, %0|%0, %2} - vp\t{%2, %1, %0|%0, %1, %2}" + vp\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,maybe_evex") (set_attr "mode" "TI")]) (define_expand "mul3" @@ -8151,8 +8152,8 @@ (define_insn "*mul3" [(set (match_operand:VI2_AVX2 0 "register_operand" "=x,x") - (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,x") - (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,xm")))] + (mult:VI2_AVX2 (match_operand:VI2_AVX2 1 "nonimmediate_operand" "%0,v") + (match_operand:VI2_AVX2 2 "nonimmediate_operand" "xm,vm")))] "TARGET_SSE2 && ix86_binary_operator_ok (MULT, mode, operands)" "@ pmullw\t{%2, %0|%0, %2} @@ -11318,7 +11319,7 @@ ;; ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -(define_expand "_uavg3" +(define_expand "_uavg3" [(set (match_operand:VI12_AVX2 0 "register_operand") (truncate:VI12_AVX2 (lshiftrt: @@ -11328,34 +11329,44 @@ (match_operand:VI12_AVX2 1 "nonimmediate_operand")) (zero_extend: (match_operand:VI12_AVX2 2 "nonimmediate_operand"))) - (match_dup 3)) + (match_dup )) (const_int 1))))] - "TARGET_SSE2" + "TARGET_SSE2 && && " { + rtx tmp; + if () + tmp = operands[3]; operands[3] = CONST1_RTX(mode); ix86_fixup_binary_operands_no_copy (PLUS, mode, operands); + + if () + { + operands[5] = operands[3]; + operands[3] = tmp; + } }) -(define_insn "*_uavg3" - [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,x") +(define_insn "*_uavg3" + [(set (match_operand:VI12_AVX2 0 "register_operand" "=x,v") (truncate:VI12_AVX2 (lshiftrt: (plus: (plus: (zero_extend: - (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,x")) + (match_operand:VI12_AVX2 1 "nonimmediate_operand" "%0,v")) (zero_extend: - (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,xm"))) - (match_operand:VI12_AVX2 3 "const1_operand")) + (match_operand:VI12_AVX2 2 "nonimmediate_operand" "xm,vm"))) + (match_operand:VI12_AVX2 "const1_operand")) (const_int 1))))] - "TARGET_SSE2 && ix86_binary_operator_ok (PLUS, mode, operands)" + "TARGET_SSE2 && && + && ix86_binary_operator_ok (PLUS, mode, operands)" "@ pavg\t{%2, %0|%0, %2} - vpavg\t{%2, %1, %0|%0, %1, %2}" + vpavg\t{%2, %1, %0|%0, %1, %2}" [(set_attr "isa" "noavx,avx") (set_attr "type" "sseiadd") (set_attr "prefix_data16" "1,*") - (set_attr "prefix" "orig,vex") + (set_attr "prefix" "orig,") (set_attr "mode" "")]) ;; The correct representation for this is absolutely enormous, and