Patchwork [V2,19/20] pci: pci bridge related clean up.

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Submitter Isaku Yamahata
Date Nov. 13, 2009, 4:29 a.m.
Message ID <1258086596-3584-20-git-send-email-yamahata@valinux.co.jp>
Download mbox | patch
Permalink /patch/38324/
State New
Headers show

Comments

Isaku Yamahata - Nov. 13, 2009, 4:29 a.m.
- fix bridge prefetchable memory accesser to check 64bit or not.
- use pcibus_t consistently instead mixing pcibus_t and uint64_t.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Acked-by: Michael S. Tsirkin <mst@redhat.com>
---
 hw/pci.c |   18 +++++++++++-------
 hw/pci.h |    1 +
 2 files changed, 12 insertions(+), 7 deletions(-)

Patch

diff --git a/hw/pci.c b/hw/pci.c
index ec3acdf..7d930eb 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -634,19 +634,23 @@  static uint32_t pci_config_get_io_base(PCIDevice *d,
     return val;
 }
 
-static uint64_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
+static pcibus_t pci_config_get_memory_base(PCIDevice *d, uint32_t base)
 {
-    return ((uint64_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
+    return ((pcibus_t)pci_get_word(d->config + base) & PCI_MEMORY_RANGE_MASK)
         << 16;
 }
 
-static uint64_t pci_config_get_pref_base(PCIDevice *d,
+static pcibus_t pci_config_get_pref_base(PCIDevice *d,
                                          uint32_t base, uint32_t upper)
 {
-    uint64_t val;
-    val = ((uint64_t)pci_get_word(d->config + base) &
-           PCI_PREF_RANGE_MASK) << 16;
-    val |= (uint64_t)pci_get_long(d->config + upper) << 32;
+    pcibus_t tmp;
+    pcibus_t val;
+
+    tmp = (pcibus_t)pci_get_word(d->config + base);
+    val = (tmp & PCI_PREF_RANGE_MASK) << 16;
+    if (tmp & PCI_PREF_RANGE_TYPE_64) {
+        val |= (pcibus_t)pci_get_long(d->config + upper) << 32;
+    }
     return val;
 }
 
diff --git a/hw/pci.h b/hw/pci.h
index 72a476e..03639b7 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -131,6 +131,7 @@  typedef struct PCIIORegion {
 #define PCI_PREF_MEMORY_BASE    0x24    /* Prefetchable memory range behind */
 #define PCI_PREF_MEMORY_LIMIT   0x26
 #define  PCI_PREF_RANGE_MASK    (~0x0fUL)
+#define  PCI_PREF_RANGE_TYPE_64 0x01
 #define PCI_PREF_BASE_UPPER32   0x28    /* Upper half of prefetchable memory range */
 #define PCI_PREF_LIMIT_UPPER32	0x2c
 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c    /* 16 bits */