| Message ID | 1408984457-10272-2-git-send-email-fabio.estevam@freescale.com |
|---|---|
| State | Awaiting Upstream |
| Delegated to: | Stefano Babic |
| Headers | show |
On Monday, August 25, 2014 at 06:34:17 PM, Fabio Estevam wrote: > When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets > always cleared prior then the READY bit is cleared in the last BD, which > causes FEC packets reception to always fail. > > As explained by Ye Li: > > "The TDAR bit is cleared when the descriptors are all out from TX ring, but > on mx6solox we noticed that the READY bit is still not cleared right after > TDAR. These are two distinct signals, and in IC simulation, we found that > TDAR always gets cleared prior than the READY bit of last BD becomes > cleared. > In mx6solox, we use a later version of FEC IP. It looks like that this > intrinsic behaviour of TDAR bit has changed in this newer FEC version." > > Fix this by polling the READY bit of BD after the TDAR polling, which > covers the mx6solox case and does not harm the other SoCs. > > No performance drop has been noticed with this patch applied when testing > TFTP transfers on several boards of different i.mx SoCs. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Acked-by: Marek Vasut <marex@denx.de> Best regards, Marek Vasut
On 25/08/2014 18:34, Fabio Estevam wrote: > When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets > always cleared prior then the READY bit is cleared in the last BD, which causes > FEC packets reception to always fail. > > As explained by Ye Li: > > "The TDAR bit is cleared when the descriptors are all out from TX ring, but on > mx6solox we noticed that the READY bit is still not cleared right after TDAR. > These are two distinct signals, and in IC simulation, we found that TDAR always > gets cleared prior than the READY bit of last BD becomes cleared. > In mx6solox, we use a later version of FEC IP. It looks like that this > intrinsic behaviour of TDAR bit has changed in this newer FEC version." > > Fix this by polling the READY bit of BD after the TDAR polling, which covers the > mx6solox case and does not harm the other SoCs. > > No performance drop has been noticed with this patch applied when testing TFTP > transfers on several boards of different i.mx SoCs. > > Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> > --- Applied to u-boot-imx, thanks ! Best regards, Stefano Babic
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index d310016..549d648 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -719,13 +719,37 @@ static int fec_send(struct eth_device *dev, void *packet, int length) break; } - if (!timeout) + if (!timeout) { ret = -EINVAL; + goto out; + } - invalidate_dcache_range(addr, addr + size); - if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY) + /* + * The TDAR bit is cleared when the descriptors are all out from TX + * but on mx6solox we noticed that the READY bit is still not cleared + * right after TDAR. + * These are two distinct signals, and in IC simulation, we found that + * TDAR always gets cleared prior than the READY bit of last BD becomes + * cleared. + * In mx6solox, we use a later version of FEC IP. It looks like that + * this intrinsic behaviour of TDAR bit has changed in this newer FEC + * version. + * + * Fix this by polling the READY bit of BD after the TDAR polling, + * which covers the mx6solox case and does not harm the other SoCs. + */ + timeout = FEC_XFER_TIMEOUT; + while (--timeout) { + invalidate_dcache_range(addr, addr + size); + if (!(readw(&fec->tbd_base[fec->tbd_index].status) & + FEC_TBD_READY)) + break; + } + + if (!timeout) ret = -EINVAL; +out: debug("fec_send: status 0x%x index %d ret %i\n", readw(&fec->tbd_base[fec->tbd_index].status), fec->tbd_index, ret);
When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets always cleared prior then the READY bit is cleared in the last BD, which causes FEC packets reception to always fail. As explained by Ye Li: "The TDAR bit is cleared when the descriptors are all out from TX ring, but on mx6solox we noticed that the READY bit is still not cleared right after TDAR. These are two distinct signals, and in IC simulation, we found that TDAR always gets cleared prior than the READY bit of last BD becomes cleared. In mx6solox, we use a later version of FEC IP. It looks like that this intrinsic behaviour of TDAR bit has changed in this newer FEC version." Fix this by polling the READY bit of BD after the TDAR polling, which covers the mx6solox case and does not harm the other SoCs. No performance drop has been noticed with this patch applied when testing TFTP transfers on several boards of different i.mx SoCs. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> --- Changes since v6: - Fix checkpatch complaint about >80 colummn Changes since v5: - Put explanation why we need to poll READY bit after TDAR into the code drivers/net/fec_mxc.c | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-)