Message ID | 1408902746-12008-2-git-send-email-festevam@gmail.com |
---|---|
State | Changes Requested |
Delegated to: | Stefano Babic |
Headers | show |
On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote: [...] > --- a/arch/arm/cpu/armv7/mx6/clock.c > +++ b/arch/arm/cpu/armv7/mx6/clock.c > @@ -504,10 +504,19 @@ int enable_pcie_clock(void) > #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) > #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) > #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F > +#ifndef CONFIG_MX6SX > + /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */ > clrsetbits_le32(&anatop_regs->ana_misc1, > ANADIG_ANA_MISC1_LVDSCLK1_IBEN | > ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, > ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); > +#else > + /* lvds_clk1 is sourced from pcie ref on imx6sx */ > + clrsetbits_le32(&anatop_regs->ana_misc1, > + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | > + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, > + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa); > +#endif Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for please ? > /* PCIe reference clock sourced from AXI. */ > clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); [...] Best regards, Marek Vasut
On Mon, Aug 25, 2014 at 4:54 AM, Marek Vasut <marex@denx.de> wrote: > On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote: > > [...] > >> --- a/arch/arm/cpu/armv7/mx6/clock.c >> +++ b/arch/arm/cpu/armv7/mx6/clock.c >> @@ -504,10 +504,19 @@ int enable_pcie_clock(void) >> #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) >> #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) >> #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F >> +#ifndef CONFIG_MX6SX >> + /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */ >> clrsetbits_le32(&anatop_regs->ana_misc1, >> ANADIG_ANA_MISC1_LVDSCLK1_IBEN | >> ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, >> ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); >> +#else >> + /* lvds_clk1 is sourced from pcie ref on imx6sx */ >> + clrsetbits_le32(&anatop_regs->ana_misc1, >> + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | >> + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, >> + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa); >> +#endif > > Is that only 1-bit difference here ? What does the magic 0xa and 0xb stand for > please ? Correct. 0xa means that LVDS1_CLK_SEL comes from PCIE_REF — PCIe ref clock 0xb means that LVDS1_CLK_SEL comes from SATA_REF — SATA ref clock In this patch I have added comments for both cases, so hopefully it is clear.
On Monday, August 25, 2014 at 03:54:29 PM, Fabio Estevam wrote: > On Mon, Aug 25, 2014 at 4:54 AM, Marek Vasut <marex@denx.de> wrote: > > On Sunday, August 24, 2014 at 07:52:25 PM, Fabio Estevam wrote: > > > > [...] > > > >> --- a/arch/arm/cpu/armv7/mx6/clock.c > >> +++ b/arch/arm/cpu/armv7/mx6/clock.c > >> @@ -504,10 +504,19 @@ int enable_pcie_clock(void) > >> > >> #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) > >> #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) > >> #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F > >> > >> +#ifndef CONFIG_MX6SX > >> + /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */ > >> > >> clrsetbits_le32(&anatop_regs->ana_misc1, > >> > >> ANADIG_ANA_MISC1_LVDSCLK1_IBEN | > >> ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, > >> ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); > >> > >> +#else > >> + /* lvds_clk1 is sourced from pcie ref on imx6sx */ > >> + clrsetbits_le32(&anatop_regs->ana_misc1, > >> + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | > >> + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, > >> + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa); > >> +#endif > > > > Is that only 1-bit difference here ? What does the magic 0xa and 0xb > > stand for please ? > > Correct. > > 0xa means that LVDS1_CLK_SEL comes from PCIE_REF — PCIe ref clock > > 0xb means that LVDS1_CLK_SEL comes from SATA_REF — SATA ref clock > > In this patch I have added comments for both cases, so hopefully it is > clear. Can you maybe pull the mask out and just ORR it with the correct bit in the ifdef ? Or -- even better, can this not be done at runtime ? Best regards, Marek Vasut
On Mon, Aug 25, 2014 at 11:27 AM, Marek Vasut <marex@denx.de> wrote: > Can you maybe pull the mask out and just ORR it with the correct bit in the > ifdef ? Or -- even better, can this not be done at runtime ? Yes, I implemented the run-time approach in v3. Thanks
diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index abd9d61..dd628d8 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -504,10 +504,19 @@ int enable_pcie_clock(void) #define ANADIG_ANA_MISC1_LVDSCLK1_IBEN (1 << 12) #define ANADIG_ANA_MISC1_LVDSCLK1_OBEN (1 << 10) #define ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK 0x0000001F +#ifndef CONFIG_MX6SX + /* lvds_clk1 is sourced from sata ref on imx6q/dl/solo */ clrsetbits_le32(&anatop_regs->ana_misc1, ANADIG_ANA_MISC1_LVDSCLK1_IBEN | ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xb); +#else + /* lvds_clk1 is sourced from pcie ref on imx6sx */ + clrsetbits_le32(&anatop_regs->ana_misc1, + ANADIG_ANA_MISC1_LVDSCLK1_IBEN | + ANADIG_ANA_MISC1_LVDS1_CLK_SEL_MASK, + ANADIG_ANA_MISC1_LVDSCLK1_OBEN | 0xa); +#endif /* PCIe reference clock sourced from AXI. */ clrbits_le32(&ccm_regs->cbcmr, MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL); diff --git a/arch/arm/include/asm/arch-mx6/iomux.h b/arch/arm/include/asm/arch-mx6/iomux.h index 6a4a632..c86aa31 100644 --- a/arch/arm/include/asm/arch-mx6/iomux.h +++ b/arch/arm/include/asm/arch-mx6/iomux.h @@ -19,6 +19,12 @@ #define IOMUXC_GPR1_TEST_POWERDOWN (1 << 18) /* + * IOMUXC_GPR5 bit fields + */ +#define IOMUXC_GPR5_PCIE_BTNRST (1 << 19) +#define IOMUXC_GPR5_PCIE_PERST (1 << 18) + +/* * IOMUXC_GPR8 bit fields */ #define IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_MASK (0x3f << 0) @@ -35,12 +41,15 @@ /* * IOMUXC_GPR12 bit fields */ +#define IOMUXC_GPR12_RX_EQ_2 (0x2 << 0) +#define IOMUXC_GPR12_RX_EQ_MASK (0x7 << 0) #define IOMUXC_GPR12_LOS_LEVEL_9 (0x9 << 4) #define IOMUXC_GPR12_LOS_LEVEL_MASK (0x1f << 4) #define IOMUXC_GPR12_APPS_LTSSM_ENABLE (1 << 10) #define IOMUXC_GPR12_DEVICE_TYPE_EP (0x0 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_RC (0x4 << 12) #define IOMUXC_GPR12_DEVICE_TYPE_MASK (0xf << 12) +#define IOMUXC_GPR12_TEST_POWERDOWN (1 << 30) /* * IOMUXC_GPR13 bit fields diff --git a/drivers/pci/pcie_imx.c b/drivers/pci/pcie_imx.c index a3982c4..194da2e 100644 --- a/drivers/pci/pcie_imx.c +++ b/drivers/pci/pcie_imx.c @@ -23,13 +23,20 @@ #define PCI_ACCESS_READ 0 #define PCI_ACCESS_WRITE 1 +#ifdef CONFIG_MX6SX +#define MX6_DBI_ADDR 0x08ffc000 +#define MX6_IO_ADDR 0x08000000 +#define MX6_MEM_ADDR 0x08100000 +#define MX6_ROOT_ADDR 0x08f00000 +#else #define MX6_DBI_ADDR 0x01ffc000 -#define MX6_DBI_SIZE 0x4000 #define MX6_IO_ADDR 0x01000000 -#define MX6_IO_SIZE 0x100000 #define MX6_MEM_ADDR 0x01100000 -#define MX6_MEM_SIZE 0xe00000 #define MX6_ROOT_ADDR 0x01f00000 +#endif +#define MX6_DBI_SIZE 0x4000 +#define MX6_IO_SIZE 0x100000 +#define MX6_MEM_SIZE 0xe00000 #define MX6_ROOT_SIZE 0xfc000 /* PCIe Port Logic registers (memory-mapped) */ @@ -57,6 +64,8 @@ #define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) #define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) +#define PCIE_PHY_PUP_REQ (1 << 7) + /* iATU registers */ #define PCIE_ATU_VIEWPORT 0x900 #define PCIE_ATU_REGION_INBOUND (0x1 << 31) @@ -421,9 +430,19 @@ static int imx_pcie_write_config(struct pci_controller *hose, pci_dev_t d, static int imx6_pcie_assert_core_reset(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - +#if defined(CONFIG_MX6SX) + struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR; + + /* SSP_EN is not used on MX6SX anymore */ + setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); + /* Force PCIe PHY reset */ + setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); + /* Power up PCIe PHY */ + setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ); +#else setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); +#endif return 0; } @@ -441,6 +460,12 @@ static int imx6_pcie_init_phy(void) IOMUXC_GPR12_LOS_LEVEL_MASK, IOMUXC_GPR12_LOS_LEVEL_9); +#ifdef CONFIG_MX6SX + clrsetbits_le32(&iomuxc_regs->gpr[12], + IOMUXC_GPR12_RX_EQ_MASK, + IOMUXC_GPR12_RX_EQ_2); +#endif + writel((0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN1_OFFSET) | (0x0 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_3P5DB_OFFSET) | (20 << IOMUXC_GPR8_PCS_TX_DEEMPH_GEN2_6DB_OFFSET) | @@ -517,9 +542,16 @@ static int imx6_pcie_deassert_core_reset(void) */ mdelay(50); +#if defined(CONFIG_MX6SX) + /* SSP_EN is not used on MX6SX anymore */ + clrbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN); + /* Clear PCIe PHY reset bit */ + clrbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST); +#else /* Enable PCIe */ clrbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_TEST_POWERDOWN); setbits_le32(&iomuxc_regs->gpr[1], IOMUXC_GPR1_REF_SSP_EN); +#endif imx6_pcie_toggle_reset();