diff mbox

[pinmux] Jetson TK1: add missing PCIe-related pin configuration

Message ID 1408741353-10259-1-git-send-email-swarren@wwwdotorg.org
State Accepted, archived
Headers show

Commit Message

Stephen Warren Aug. 22, 2014, 9:02 p.m. UTC 
From: Stephen Warren <swarren@nvidia.com>

The Jetson TK1 spreadsheet is missing configuration for the PCIe clk_req,
rst, and wake pins. This causes the generated pinmux tables to also omit
any configuration for these pins, which in turn causes U-Boot's and the
Linux Kernel's PCIe support to fail.

Manually add configuration for these pins. The values here match the
values found in the downstream L4T kernel, and common sense based on the
usage of these pins.

Signed-off-by: Stephen Warren <swarren@nvidia.com>
---
 configs/jetson-tk1.board | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Stephen Warren Aug. 25, 2014, 4:22 p.m. UTC | #1 
On 08/22/2014 03:02 PM, Stephen Warren wrote:
> From: Stephen Warren <swarren@nvidia.com>
>
> The Jetson TK1 spreadsheet is missing configuration for the PCIe clk_req,
> rst, and wake pins. This causes the generated pinmux tables to also omit
> any configuration for these pins, which in turn causes U-Boot's and the
> Linux Kernel's PCIe support to fail.
>
> Manually add configuration for these pins. The values here match the
> values found in the downstream L4T kernel, and common sense based on the
> usage of these pins.

I've applied this.
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diff mbox

Patch

diff --git a/configs/jetson-tk1.board b/configs/jetson-tk1.board
index 1df628406985..f69b89ec0af8 100644
--- a/configs/jetson-tk1.board
+++ b/configs/jetson-tk1.board
@@ -89,6 +89,11 @@  pins = (
     ('pi7',                    'rsvd1',        None,      'down', True,  False, False, False),
     ('pc7',                    None,           'in',      'up',   False, True,  False, False),
     ('pi0',                    None,           'out0',    'none', False, False, False, False),
+    ('pex_l0_clkreq_n_pdd2',   'pe0',          None,      'up',   False, True,  False, False),
+    ('pex_l0_rst_n_pdd1',      'pe0',          None,      'none', False, False, False, False),
+    ('pex_l1_clkreq_n_pdd6',   'pe1',          None,      'up',   False, True,  False, False),
+    ('pex_l1_rst_n_pdd5',      'pe1',          None,      'none', False, False, False, False),
+    ('pex_wake_n_pdd3',        'pe',           None,      'up',   False, True,  False, False),
     ('usb_vbus_en2_pff1',      None,           'out0',    'none', False, False, False, False),
     ('pff2',                   None,           'in',      'up',   False, True,  False, False),
     ('clk2_out_pw5',           'extperiph2',   None,      'none', False, False, False, False),