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[U-Boot,v5,2/2] net: fec_mxc: Poll FEC_TBD_READY after polling TDAR

Message ID 1408736439-3780-2-git-send-email-festevam@gmail.com
State Superseded
Delegated to: Stefano Babic
Headers show

Commit Message

Fabio Estevam Aug. 22, 2014, 7:40 p.m. UTC 
From: Fabio Estevam <fabio.estevam@freescale.com>

When testing the FEC driver on a mx6solox we noticed that the TDAR bit gets
always cleared prior then the READY bit is cleared in the last BD, which causes
FEC packets reception to always fail.

As explained by Ye Li:

"The TDAR bit is cleared when the descriptors are all out from TX ring, but on 
mx6solox we noticed that the READY bit is still not cleared right after TDAR. 
These are two distinct signals, and in IC simulation, we found that TDAR always
gets cleared prior than the READY bit of last BD becomes cleared. 
In mx6solox, we use a later version of FEC IP. It looks like that this 
intrinsic behaviour of TDAR bit has changed in this newer FEC version."

Fix this by polling the READY bit of BD after the TDAR polling, which covers the
mx6solox case and does not harm the other SoCs.

No performance drop has been noticed with this patch applied when testing TFTP
transfers on several boards of different i.mx SoCs.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
---
Changes since v4:
- Improve wording in the commit log.

 drivers/net/fec_mxc.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)
diff mbox

Patch

diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index 56178d4..4bfd625 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -719,13 +719,22 @@  static int fec_send(struct eth_device *dev, void *packet, int length)
 			break;
 	}
 
-	if (!timeout)
+	if (!timeout) {
 		ret = -EINVAL;
+		goto out;
+	}
 
-	invalidate_dcache_range(addr, addr + size);
-	if (readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY)
+	timeout = FEC_XFER_TIMEOUT;
+	while (--timeout) {
+		invalidate_dcache_range(addr, addr + size);
+		if (!(readw(&fec->tbd_base[fec->tbd_index].status) & FEC_TBD_READY))
+			break;
+	}
+
+	if (!timeout)
 		ret = -EINVAL;
 
+out:
 	debug("fec_send: status 0x%x index %d ret %i\n",
 			readw(&fec->tbd_base[fec->tbd_index].status),
 			fec->tbd_index, ret);