| Message ID | 53F740F7.2010706@gmail.com |
|---|---|
| State | New |
| Headers | show |
Hi, I would like to share this series of patches to improve the openrisc machine. Mostly my goal is to have the same features as the web based machine and be able to boot qemu with exactly the same images. Some feedback would be appreciated. Regards, Valentin
Hi Valentin, On Fri, Aug 22, 2014 at 10:01 PM, Valentin Manea <valentin.manea@gmail.com> wrote: > Hi, > > I would like to share this series of patches to improve the openrisc > machine. Mostly my goal is to have the same features as the web based > machine and be able to boot qemu with exactly the same images. > Some feedback would be appreciated. Thank you very much! May you please upload the test linux image to somewhere, and tell us your test steps? Make me can test your change. > > Regards, > Valentin Regards, Jia
Hi Jia, On 2014-08-22 19:11, Jia Liu wrote: > Hi Valentin, > > Thank you very much! > May you please upload the test linux image to somewhere, and tell us > your test steps? > Make me can test your change. I've resent the patches including the needed images(vmlinux and hdX). Please note that you also need the patch IDE: MMIO IDE device control should be little endian I sent earlier to make sure the MMIO IDE device works for OpenRisc. Valentin
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak index cce4746..c3ff078 100644 --- a/default-configs/or32-softmmu.mak +++ b/default-configs/or32-softmmu.mak @@ -2,3 +2,6 @@ CONFIG_SERIAL=y CONFIG_OPENCORES_ETH=y +CONFIG_IDE_CORE=y +CONFIG_IDE_QDEV=y +CONFIG_IDE_MMIO=y diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index b2b4f9b..da8647f 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -24,9 +24,11 @@ #include "hw/char/serial.h" #include "net/net.h" #include "hw/loader.h" +#include "hw/ide.h" #include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" +#include "sysemu/blockdev.h" #include "sysemu/qtest.h" #define KERNEL_LOAD_ADDR 0x100 @@ -38,6 +40,32 @@ static void main_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +static void openrisc_sim_ide_init(MemoryRegion *address_space, + hwaddr base, + hwaddr descriptors, + qemu_irq irq) +{ + DeviceState *dev; + SysBusDevice *busdev; + DriveInfo *dinfo; + + + dinfo = drive_get(IF_IDE, 0, 0); + if (!dinfo) { + return; + } + dev = qdev_create(NULL, "mmio-ide"); + busdev = SYS_BUS_DEVICE(dev); + sysbus_connect_irq(busdev, 0, irq); + qdev_prop_set_uint32(dev, "shift", 2); + qdev_init_nofail(dev); + memory_region_add_subregion(address_space, base, + sysbus_mmio_get_region(busdev, 0)); + memory_region_add_subregion(address_space, descriptors, + sysbus_mmio_get_region(busdev, 1)); + mmio_ide_init_drives(dev, dinfo, NULL); +} + static void openrisc_sim_net_init(MemoryRegion *address_space, hwaddr base, hwaddr descriptors, @@ -129,6 +157,10 @@ static void openrisc_sim_init(MachineState *machine) 0x92000400, cpu->env.irq[4], nd_table); } + /* Platform ATA device */ + openrisc_sim_ide_init(get_system_memory(), 0x9e000000, + 0x9e000100, cpu->env.irq[15]); + cpu_openrisc_load_kernel(ram_size, kernel_filename, cpu); }
Add MMIO ide device support to the default openrisc machine. Base address and IRQ line are the same as the or1ksim. Signed-off-by: Valentin Manea <valentin.manea@gmail.com> --- default-configs/or32-softmmu.mak | 3 +++ hw/openrisc/openrisc_sim.c | 32 ++++++++++++++++++++++++++++++++ 2 files changed, 35 insertions(+)