diff mbox

[U-Boot,v3,1/2] net: fec_mxc: Adjust RX DMA alignment for mx6solox

Message ID CAOMZO5DNcV1M396vwcyez22NSBpmom4xZ0QGw6Fye6VhCLGPUw@mail.gmail.com
State Superseded
Delegated to: Stefano Babic
Headers show

Commit Message

Fabio Estevam Aug. 21, 2014, 4:41 p.m. UTC 
On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut <marex@denx.de> wrote:

> Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't there
> something completely else broken on MX6SX ?

Thanks for the review, Marek.

Inspecting this further I think the correct fix would be:

 arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

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Comments

Marek Vasut Aug. 21, 2014, 5:01 p.m. UTC | #1 
On Thursday, August 21, 2014 at 06:41:26 PM, Fabio Estevam wrote:
> On Thu, Aug 21, 2014 at 1:21 PM, Marek Vasut <marex@denx.de> wrote:
> > Isn't MX6SX ARMv7 with 64-byte cacheline alignment anyway ? So isn't
> > there something completely else broken on MX6SX ?
> 
> Thanks for the review, Marek.
> 
> Inspecting this further I think the correct fix would be:
> 
>  arch/arm/include/asm/arch-mx6/imx-regs.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
> b/arch/arm/include/asm/arch-mx6/imx-regs.h
> index 2631beb..e9e6f63 100644
> --- a/arch/arm/include/asm/arch-mx6/imx-regs.h
> +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
> @@ -9,7 +9,7 @@
> 
>  #define ARCH_MXC
> 
> -#define CONFIG_SYS_CACHELINE_SIZE    32
> +#define CONFIG_SYS_CACHELINE_SIZE    64

Well yeah, it would ;-)

Best regards,
Marek Vasut
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h
b/arch/arm/include/asm/arch-mx6/imx-regs.h
index 2631beb..e9e6f63 100644
--- a/arch/arm/include/asm/arch-mx6/imx-regs.h
+++ b/arch/arm/include/asm/arch-mx6/imx-regs.h
@@ -9,7 +9,7 @@ 

 #define ARCH_MXC

-#define CONFIG_SYS_CACHELINE_SIZE    32
+#define CONFIG_SYS_CACHELINE_SIZE    64

Do you agree?
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