Message ID | 1408536546-15785-11-git-send-email-nikita@compulab.co.il |
---|---|
State | Awaiting Upstream |
Delegated to: | Stefano Babic |
Headers | show |
On 20/08/14 15:08, Nikita Kiryanov wrote: > According to MX6 TRM, both MMDC and DRAM should be configured to > the same powerdown precharge. Currently, mx6_dram_cfg() > configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for > 'slow exit (DLL off)' (MR0[12] = 0). > > Configure MMDC for slow pd. > We have confirmation from a Freescale representative that the configurations should be aligned: https://community.freescale.com/thread/328577
On Mon, Aug 25, 2014 at 8:36 AM, Nikita Kiryanov <nikita@compulab.co.il> wrote: > > On 20/08/14 15:08, Nikita Kiryanov wrote: >> >> According to MX6 TRM, both MMDC and DRAM should be configured to >> the same powerdown precharge. Currently, mx6_dram_cfg() >> configures MMDC for fast pd (MDPDC[7] = 0), and the DRAM for >> 'slow exit (DLL off)' (MR0[12] = 0). >> >> Configure MMDC for slow pd. >> > > We have confirmation from a Freescale representative that the > configurations should be aligned: > > https://community.freescale.com/thread/328577 > > -- > Regards, > Nikita Kiryanov Nikita, Yep... Acked-by: Tim Harvey <tharvey@gateworks.com> (Next I'll ask them about that delay for ZQ calibration - it bugs me that your finding you need an extra 100us delay on your boards, but that shouldn't hold up any of your patches) Tim
diff --git a/arch/arm/cpu/armv7/mx6/ddr.c b/arch/arm/cpu/armv7/mx6/ddr.c index 70ce38f..c0fb749 100644 --- a/arch/arm/cpu/armv7/mx6/ddr.c +++ b/arch/arm/cpu/armv7/mx6/ddr.c @@ -463,6 +463,7 @@ void mx6_dram_cfg(const struct mx6_ddr_sysinfo *sysinfo, mmdc0->mdpdc = (tcke & 0x7) << 16 | 5 << 12 | /* PWDT_1: 256 cycles */ 5 << 8 | /* PWDT_0: 256 cycles */ + 1 << 7 | /* SLOW_PD */ 1 << 6 | /* BOTH_CS_PD */ (tcksrx & 0x7) << 3 | (tcksre & 0x7);