| Message ID | 1407851110-8075-8-git-send-email-tommusta@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 08/12/2014 03:45 AM, Tom Musta wrote: > For 64 bit implementations, the special case of a shift by zero > should result in the sign extension of the least significant 32 bits > of the source GPR (not a direct copy of the 64 bit source GPR). > > Example: > > R3 A6212433228F41DC > srawi 3,3,0 > R3 expected : 00000000228F41DC > R3 actual : A6212433228F41DC (without this patch) Reviewed-by: Richard Henderson <rth@twiddle.net> r~
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 4904665..61fa42d 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -1941,7 +1941,7 @@ static void gen_srawi(DisasContext *ctx) TCGv dst = cpu_gpr[rA(ctx->opcode)]; TCGv src = cpu_gpr[rS(ctx->opcode)]; if (sh == 0) { - tcg_gen_mov_tl(dst, src); + tcg_gen_ext32s_tl(dst, src); tcg_gen_movi_tl(cpu_ca, 0); } else { TCGv t0;
For 64 bit implementations, the special case of a shift by zero should result in the sign extension of the least significant 32 bits of the source GPR (not a direct copy of the 64 bit source GPR). Example: R3 A6212433228F41DC srawi 3,3,0 R3 expected : 00000000228F41DC R3 actual : A6212433228F41DC (without this patch) Signed-off-by: Tom Musta <tommusta@gmail.com> --- target-ppc/translate.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)