@@ -17,16 +17,16 @@ Required properties:
5th optional memory resource shall be the host
controller MUX memory resource if required.
- interrupts : Interrupt-specifier for SATA host controller IRQ.
-- clocks : Reference to the clock entry.
-- phys : A list of phandles + phy-specifiers, one for each
- entry in phy-names.
-- phy-names : Should contain:
- * "sata-phy" for the SATA 6.0Gbps PHY
Optional properties:
- dma-coherent : Present if dma operations are coherent
- status : Shall be "ok" if enabled or "disabled" if disabled.
Default is "ok".
+- clocks : Reference to the clock entry.
+- phys : A list of phandles + phy-specifiers, one for each
+ entry in phy-names.
+- phy-names : Should contain:
+ * "sata-phy" for the SATA 6.0Gbps PHY
Example:
sataclk: sataclk {
@@ -177,87 +177,6 @@
clock-output-names = "eth8clk";
};
- sataphy1clk: sataphy1clk@1f21c000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&socplldiv2 0>;
- reg = <0x0 0x1f21c000 0x0 0x1000>;
- reg-names = "csr-reg";
- clock-output-names = "sataphy1clk";
- status = "disabled";
- csr-offset = <0x4>;
- csr-mask = <0x00>;
- enable-offset = <0x0>;
- enable-mask = <0x06>;
- };
-
- sataphy2clk: sataphy1clk@1f22c000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&socplldiv2 0>;
- reg = <0x0 0x1f22c000 0x0 0x1000>;
- reg-names = "csr-reg";
- clock-output-names = "sataphy2clk";
- status = "ok";
- csr-offset = <0x4>;
- csr-mask = <0x3a>;
- enable-offset = <0x0>;
- enable-mask = <0x06>;
- };
-
- sataphy3clk: sataphy1clk@1f23c000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&socplldiv2 0>;
- reg = <0x0 0x1f23c000 0x0 0x1000>;
- reg-names = "csr-reg";
- clock-output-names = "sataphy3clk";
- status = "ok";
- csr-offset = <0x4>;
- csr-mask = <0x3a>;
- enable-offset = <0x0>;
- enable-mask = <0x06>;
- };
-
- sata01clk: sata01clk@1f21c000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&socplldiv2 0>;
- reg = <0x0 0x1f21c000 0x0 0x1000>;
- reg-names = "csr-reg";
- clock-output-names = "sata01clk";
- csr-offset = <0x4>;
- csr-mask = <0x05>;
- enable-offset = <0x0>;
- enable-mask = <0x39>;
- };
-
- sata23clk: sata23clk@1f22c000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&socplldiv2 0>;
- reg = <0x0 0x1f22c000 0x0 0x1000>;
- reg-names = "csr-reg";
- clock-output-names = "sata23clk";
- csr-offset = <0x4>;
- csr-mask = <0x05>;
- enable-offset = <0x0>;
- enable-mask = <0x39>;
- };
-
- sata45clk: sata45clk@1f23c000 {
- compatible = "apm,xgene-device-clock";
- #clock-cells = <1>;
- clocks = <&socplldiv2 0>;
- reg = <0x0 0x1f23c000 0x0 0x1000>;
- reg-names = "csr-reg";
- clock-output-names = "sata45clk";
- csr-offset = <0x4>;
- csr-mask = <0x05>;
- enable-offset = <0x0>;
- enable-mask = <0x39>;
- };
-
rtcclk: rtcclk@17000000 {
compatible = "apm,xgene-device-clock";
#clock-cells = <1>;
@@ -320,7 +239,6 @@
compatible = "apm,xgene-phy";
reg = <0x0 0x1f21a000 0x0 0x100>;
#phy-cells = <1>;
- clocks = <&sataphy1clk 0>;
status = "disabled";
apm,tx-boost-gain = <30 30 30 30 30 30>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
@@ -330,7 +248,6 @@
compatible = "apm,xgene-phy";
reg = <0x0 0x1f22a000 0x0 0x100>;
#phy-cells = <1>;
- clocks = <&sataphy2clk 0>;
status = "ok";
apm,tx-boost-gain = <30 30 30 30 30 30>;
apm,tx-eye-tuning = <1 10 10 2 10 10>;
@@ -340,7 +257,6 @@
compatible = "apm,xgene-phy";
reg = <0x0 0x1f23a000 0x0 0x100>;
#phy-cells = <1>;
- clocks = <&sataphy3clk 0>;
status = "ok";
apm,tx-boost-gain = <31 31 31 31 31 31>;
apm,tx-eye-tuning = <2 10 10 2 10 10>;
@@ -356,9 +272,6 @@
interrupts = <0x0 0x86 0x4>;
dma-coherent;
status = "disabled";
- clocks = <&sata01clk 0>;
- phys = <&phy1 0>;
- phy-names = "sata-phy";
};
sata2: sata@1a400000 {
@@ -371,9 +284,6 @@
interrupts = <0x0 0x87 0x4>;
dma-coherent;
status = "ok";
- clocks = <&sata23clk 0>;
- phys = <&phy2 0>;
- phy-names = "sata-phy";
};
sata3: sata@1a800000 {
@@ -385,9 +295,6 @@
interrupts = <0x0 0x88 0x4>;
dma-coherent;
status = "ok";
- clocks = <&sata45clk 0>;
- phys = <&phy3 0>;
- phy-names = "sata-phy";
};
rtc: rtc@10510000 {