| Message ID | 197B3989-3373-4172-B5FA-727CA1EEE2AA@kernel.crashing.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
On Nov 5, 2009, at 7:58 AM, Kumar Gala wrote: > > On Sep 15, 2009, at 4:43 PM, Anton Vorontsov wrote: > >> - Add power management controller nodes; >> - Add interrupts for RTC nodes, the RTC interrupt may be used as a >> wakeup source; >> - Add sleep properties and sleep-nexus nodes. >> >> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> >> Acked-by: Scott Wood <scottwood@freescale.com> >> --- >> arch/powerpc/boot/dts/mpc8568mds.dts | 119 ++++++++++++++++++ >> +---------- >> arch/powerpc/boot/dts/mpc8569mds.dts | 111 +++++++++++++++++ >> +--------- >> arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 + >> 3 files changed, 153 insertions(+), 78 deletions(-) > > diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/ > boot/dts/mpc8568mds.dts > index 00c2bbd..6d892ba 100644 > --- a/arch/powerpc/boot/dts/mpc8568mds.dts > +++ b/arch/powerpc/boot/dts/mpc8568mds.dts > @@ -40,6 +40,8 @@ > i-cache-line-size = <32>; // 32 bytes > d-cache-size = <0x8000>; // L1, 32K > i-cache-size = <0x8000>; // L1, 32K > + sleep = <&pmc 0x00008000 // core > + &pmc 0x00004000>; // timebase > > Just so I'm clear this is the devdisr bit position? Also where in the code do we use this? I'm not seeing it. - k
On Thu, Nov 05, 2009 at 07:58:49AM -0600, Kumar Gala wrote: [...] > --- a/arch/powerpc/boot/dts/mpc8568mds.dts > +++ b/arch/powerpc/boot/dts/mpc8568mds.dts > @@ -40,6 +40,8 @@ > i-cache-line-size = <32>; // 32 bytes > d-cache-size = <0x8000>; // L1, 32K > i-cache-size = <0x8000>; // L1, 32K > + sleep = <&pmc 0x00008000 // core > + &pmc 0x00004000>; // timebase > > Just so I'm clear this is the devdisr bit position? Yep, as described in the bindings. Thanks,
On Nov 5, 2009, at 8:04 AM, Anton Vorontsov wrote: > On Thu, Nov 05, 2009 at 07:58:49AM -0600, Kumar Gala wrote: > [...] >> --- a/arch/powerpc/boot/dts/mpc8568mds.dts >> +++ b/arch/powerpc/boot/dts/mpc8568mds.dts >> @@ -40,6 +40,8 @@ >> i-cache-line-size = <32>; // 32 bytes >> d-cache-size = <0x8000>; // L1, 32K >> i-cache-size = <0x8000>; // L1, 32K >> + sleep = <&pmc 0x00008000 // core >> + &pmc 0x00004000>; // timebase >> >> Just so I'm clear this is the devdisr bit position? > > Yep, as described in the bindings. I don't think the binding is clear that for 85xx these are DEVDISR bit positions for the given SoC. - k
On Thu, Nov 05, 2009 at 08:02:44AM -0600, Kumar Gala wrote: [...] > >diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/ > >boot/dts/mpc8568mds.dts > >index 00c2bbd..6d892ba 100644 > >--- a/arch/powerpc/boot/dts/mpc8568mds.dts > >+++ b/arch/powerpc/boot/dts/mpc8568mds.dts > >@@ -40,6 +40,8 @@ > > i-cache-line-size = <32>; // 32 bytes > > d-cache-size = <0x8000>; // L1, 32K > > i-cache-size = <0x8000>; // L1, 32K > >+ sleep = <&pmc 0x00008000 // core > >+ &pmc 0x00004000>; // timebase > > > >Just so I'm clear this is the devdisr bit position? > > Also where in the code do we use this? I'm not seeing it. We don't use it (yet). The per-device power management is not yet implemented. It is relatively easy to do on 83xx, but on 85xx there is a restriction: we can't re-enable the device after we disable it, i.e. POR sequence is needed. Though, we may want to disable all 'unused' (say echo 1 > /sys/devices/.../permanently_disable) to save some power. Thanks,
On Thu, Nov 05, 2009 at 08:06:51AM -0600, Kumar Gala wrote: > > On Nov 5, 2009, at 8:04 AM, Anton Vorontsov wrote: > >> On Thu, Nov 05, 2009 at 07:58:49AM -0600, Kumar Gala wrote: >> [...] >>> --- a/arch/powerpc/boot/dts/mpc8568mds.dts >>> +++ b/arch/powerpc/boot/dts/mpc8568mds.dts >>> @@ -40,6 +40,8 @@ >>> i-cache-line-size = <32>; // 32 bytes >>> d-cache-size = <0x8000>; // L1, 32K >>> i-cache-size = <0x8000>; // L1, 32K >>> + sleep = <&pmc 0x00008000 // core >>> + &pmc 0x00004000>; // timebase >>> >>> Just so I'm clear this is the devdisr bit position? >> >> Yep, as described in the bindings. > > I don't think the binding is clear that for 85xx these are DEVDISR bit > positions for the given SoC. From dts-bindings/fsl/pmc.txt: fsl,mpc8548-pmc: Sleep specifiers consist of one or two cells, the first of which will be ORed into DEVDISR (and the second into DEVDISR2, if present -- this cell should be zero or absent if the hardware does not have DEVDISR2) upon a request for permanent device disabling. This sleep controller does not support configuring devices to disable during system sleep (unless supported by another compatible match), or dynamically. -Scott
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts b/arch/powerpc/boot/ dts/mpc8568mds.dts index 00c2bbd..6d892ba 100644 --- a/arch/powerpc/boot/dts/mpc8568mds.dts +++ b/arch/powerpc/boot/dts/mpc8568mds.dts @@ -40,6 +40,8 @@ i-cache-line-size = <32>; // 32 bytes d-cache-size = <0x8000>; // L1, 32K i-cache-size = <0x8000>; // L1, 32K + sleep = <&pmc 0x00008000 // core + &pmc 0x00004000>; // timebase Just so I'm clear this is the devdisr bit position?