@@ -42,10 +42,10 @@ extern void tilegx_expand_umuldi3_highpart (rtx, rtx, rtx);
extern bool tilegx_emit_setcc (rtx[], enum machine_mode);
extern void tilegx_emit_conditional_branch (rtx[], enum machine_mode);
extern rtx tilegx_emit_conditional_move (rtx);
-extern const char *tilegx_output_cbranch_with_opcode (rtx, rtx *,
+extern const char *tilegx_output_cbranch_with_opcode (rtx_insn *, rtx *,
const char *,
const char *, int);
-extern const char *tilegx_output_cbranch (rtx, rtx *, bool);
+extern const char *tilegx_output_cbranch (rtx_insn *, rtx *, bool);
extern void tilegx_expand_tablejump (rtx, rtx);
extern void tilegx_expand_builtin_vector_binop (rtx (*)(rtx, rtx, rtx),
enum machine_mode, rtx,
@@ -61,10 +61,10 @@ extern void tilegx_expand_epilogue (bool);
extern int tilegx_initial_elimination_offset (int, int);
extern rtx tilegx_return_addr (int, rtx);
extern rtx tilegx_eh_return_handler_rtx (void);
-extern int tilegx_adjust_insn_length (rtx, int);
+extern int tilegx_adjust_insn_length (rtx_insn *, int);
extern int tilegx_asm_preferred_eh_data_format (int, int);
-extern void tilegx_final_prescan_insn (rtx);
+extern void tilegx_final_prescan_insn (rtx_insn *);
extern const char *tilegx_asm_output_opcode (FILE *, const char *);
extern void tilegx_function_profiler (FILE *, int);
@@ -1041,7 +1041,8 @@ tilegx_legitimize_tls_address (rtx addr)
}
case TLS_MODEL_INITIAL_EXEC:
{
- rtx temp, temp2, temp3, got, last;
+ rtx temp, temp2, temp3, got;
+ rtx_insn *last;
ret = gen_reg_rtx (Pmode);
temp = gen_reg_rtx (Pmode);
@@ -1075,7 +1076,8 @@ tilegx_legitimize_tls_address (rtx addr)
}
case TLS_MODEL_LOCAL_EXEC:
{
- rtx temp, temp2, last;
+ rtx temp, temp2;
+ rtx_insn *last;
ret = gen_reg_rtx (Pmode);
temp = gen_reg_rtx (Pmode);
@@ -2619,7 +2621,7 @@ tilegx_emit_conditional_move (rtx cmp)
/* Return true if INSN is annotated with a REG_BR_PROB note that
indicates it's a branch that's predicted taken. */
static bool
-cbranch_predicted_p (rtx insn)
+cbranch_predicted_p (rtx_insn *insn)
{
rtx x = find_reg_note (insn, REG_BR_PROB, 0);
@@ -2637,7 +2639,7 @@ cbranch_predicted_p (rtx insn)
/* Output assembly code for a specific branch instruction, appending
the branch prediction flag to the opcode if appropriate. */
static const char *
-tilegx_output_simple_cbranch_with_opcode (rtx insn, const char *opcode,
+tilegx_output_simple_cbranch_with_opcode (rtx_insn *insn, const char *opcode,
int regop, bool reverse_predicted)
{
static char buf[64];
@@ -2651,7 +2653,7 @@ tilegx_output_simple_cbranch_with_opcode (rtx insn, const char *opcode,
/* Output assembly code for a specific branch instruction, appending
the branch prediction flag to the opcode if appropriate. */
const char *
-tilegx_output_cbranch_with_opcode (rtx insn, rtx *operands,
+tilegx_output_cbranch_with_opcode (rtx_insn *insn, rtx *operands,
const char *opcode,
const char *rev_opcode, int regop)
{
@@ -2699,7 +2701,7 @@ tilegx_output_cbranch_with_opcode (rtx insn, rtx *operands,
/* Output assembly code for a conditional branch instruction. */
const char *
-tilegx_output_cbranch (rtx insn, rtx *operands, bool reversed)
+tilegx_output_cbranch (rtx_insn *insn, rtx *operands, bool reversed)
{
enum rtx_code code = GET_CODE (operands[1]);
const char *opcode;
@@ -3757,7 +3759,7 @@ frame_emit_store (int regno, int regno_note, rtx addr, rtx cfa,
/* Emit a load in the stack frame to load REGNO from address ADDR.
Add a REG_CFA_RESTORE note to CFA_RESTORES if CFA_RESTORES is
non-null. Return the emitted insn. */
-static rtx
+static rtx_insn *
frame_emit_load (int regno, rtx addr, rtx *cfa_restores)
{
rtx reg = gen_rtx_REG (DImode, regno);
@@ -3773,8 +3775,8 @@ frame_emit_load (int regno, rtx addr, rtx *cfa_restores)
static rtx
set_frame_related_p (void)
{
- rtx seq = get_insns ();
- rtx insn;
+ rtx_insn *seq = get_insns ();
+ rtx_insn *insn;
end_sequence ();
@@ -3810,14 +3812,15 @@ set_frame_related_p (void)
large register and using 'add'.
This happens after reload, so we need to expand it ourselves. */
-static rtx
+static rtx_insn *
emit_sp_adjust (int offset, int *next_scratch_regno, bool frame_related,
rtx reg_notes)
{
rtx to_add;
rtx imm_rtx = GEN_INT (offset);
+ rtx pat;
+ rtx_insn *insn;
- rtx insn;
if (satisfies_constraint_J (imm_rtx))
{
/* We can add this using a single immediate add. */
@@ -3832,11 +3835,11 @@ emit_sp_adjust (int offset, int *next_scratch_regno, bool frame_related,
/* Actually adjust the stack pointer. */
if (TARGET_32BIT)
- insn = gen_sp_adjust_32bit (stack_pointer_rtx, stack_pointer_rtx, to_add);
+ pat = gen_sp_adjust_32bit (stack_pointer_rtx, stack_pointer_rtx, to_add);
else
- insn = gen_sp_adjust (stack_pointer_rtx, stack_pointer_rtx, to_add);
+ pat = gen_sp_adjust (stack_pointer_rtx, stack_pointer_rtx, to_add);
- insn = emit_insn (insn);
+ insn = emit_insn (pat);
REG_NOTES (insn) = reg_notes;
/* Describe what just happened in a way that dwarf understands. */
@@ -4148,7 +4151,7 @@ tilegx_expand_epilogue (bool sibcall_p)
rtx reg_save_addr[ROUND_ROBIN_SIZE] = {
NULL_RTX, NULL_RTX, NULL_RTX, NULL_RTX
};
- rtx last_insn, insn;
+ rtx_insn *last_insn, *insn;
unsigned int which_scratch;
int offset, start_offset, regno;
rtx cfa_restores = NULL_RTX;
@@ -4381,7 +4384,7 @@ tilegx_frame_pointer_required (void)
by attributes in the machine-description file. This is where we
account for bundles. */
int
-tilegx_adjust_insn_length (rtx insn, int length)
+tilegx_adjust_insn_length (rtx_insn *insn, int length)
{
enum machine_mode mode = GET_MODE (insn);
@@ -4446,8 +4449,8 @@ tilegx_sched_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
/* Skip over irrelevant NOTEs and such and look for the next insn we
would consider bundling. */
-static rtx
-next_insn_to_bundle (rtx r, rtx end)
+static rtx_insn *
+next_insn_to_bundle (rtx_insn *r, rtx_insn *end)
{
for (; r != end; r = NEXT_INSN (r))
{
@@ -4457,7 +4460,7 @@ next_insn_to_bundle (rtx r, rtx end)
return r;
}
- return NULL_RTX;
+ return NULL;
}
@@ -4470,10 +4473,10 @@ tilegx_gen_bundles (void)
basic_block bb;
FOR_EACH_BB_FN (bb, cfun)
{
- rtx insn, next, prev;
- rtx end = NEXT_INSN (BB_END (bb));
+ rtx_insn *insn, *next, *prev;
+ rtx_insn *end = NEXT_INSN (BB_END (bb));
- prev = NULL_RTX;
+ prev = NULL;
for (insn = next_insn_to_bundle (BB_HEAD (bb), end); insn;
prev = insn, insn = next)
{
@@ -4519,7 +4522,7 @@ tilegx_gen_bundles (void)
/* Replace OLD_INSN with NEW_INSN. */
static void
-replace_insns (rtx old_insn, rtx new_insns)
+replace_insns (rtx_insn *old_insn, rtx_insn *new_insns)
{
if (new_insns)
emit_insn_before (new_insns, old_insn);
@@ -4549,12 +4552,12 @@ match_pcrel_step1 (rtx insn)
/* Do the first replacement step in tilegx_fixup_pcrel_references. */
static void
-replace_mov_pcrel_step1 (rtx insn)
+replace_mov_pcrel_step1 (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx unspec;
rtx opnds[2];
- rtx new_insns;
+ rtx_insn *new_insns;
gcc_assert (GET_CODE (pattern) == SET);
opnds[0] = SET_DEST (pattern);
@@ -4617,13 +4620,13 @@ match_pcrel_step2 (rtx insn)
/* Do the second replacement step in tilegx_fixup_pcrel_references. */
static void
-replace_mov_pcrel_step2 (rtx insn)
+replace_mov_pcrel_step2 (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx unspec;
rtx addr;
rtx opnds[3];
- rtx new_insns;
+ rtx_insn *new_insns;
rtx got_rtx = tilegx_got_rtx ();
gcc_assert (GET_CODE (pattern) == SET);
@@ -4674,12 +4677,12 @@ replace_mov_pcrel_step2 (rtx insn)
/* Do the third replacement step in tilegx_fixup_pcrel_references. */
static void
-replace_mov_pcrel_step3 (rtx insn)
+replace_mov_pcrel_step3 (rtx_insn *insn)
{
rtx pattern = PATTERN (insn);
rtx unspec;
rtx opnds[4];
- rtx new_insns;
+ rtx_insn *new_insns;
rtx got_rtx = tilegx_got_rtx ();
rtx text_label_rtx = tilegx_text_label_rtx ();
@@ -4759,7 +4762,7 @@ replace_mov_pcrel_step3 (rtx insn)
static void
tilegx_fixup_pcrel_references (void)
{
- rtx insn, next_insn;
+ rtx_insn *insn, *next_insn;
bool same_section_as_entry = true;
for (insn = get_insns (); insn; insn = next_insn)
@@ -4810,8 +4813,8 @@ reorder_var_tracking_notes (void)
basic_block bb;
FOR_EACH_BB_FN (bb, cfun)
{
- rtx insn, next;
- rtx queue = NULL_RTX;
+ rtx_insn *insn, *next;
+ rtx_insn *queue = NULL;
bool in_bundle = false;
for (insn = BB_HEAD (bb); insn != BB_END (bb); insn = next)
@@ -4826,7 +4829,7 @@ reorder_var_tracking_notes (void)
{
while (queue)
{
- rtx next_queue = PREV_INSN (queue);
+ rtx_insn *next_queue = PREV_INSN (queue);
SET_PREV_INSN (NEXT_INSN (insn)) = queue;
SET_NEXT_INSN (queue) = NEXT_INSN (insn);
SET_NEXT_INSN (insn) = queue;
@@ -4842,7 +4845,7 @@ reorder_var_tracking_notes (void)
{
if (in_bundle)
{
- rtx prev = PREV_INSN (insn);
+ rtx_insn *prev = PREV_INSN (insn);
SET_PREV_INSN (next) = prev;
SET_NEXT_INSN (prev) = next;
@@ -4916,7 +4919,8 @@ tilegx_output_mi_thunk (FILE *file, tree thunk_fndecl ATTRIBUTE_UNUSED,
HOST_WIDE_INT delta, HOST_WIDE_INT vcall_offset,
tree function)
{
- rtx this_rtx, insn, funexp, addend;
+ rtx this_rtx, funexp, addend;
+ rtx_insn *insn;
/* Pretend to be a post-reload pass while generating rtl. */
reload_completed = 1;
@@ -5462,7 +5466,7 @@ static enum machine_mode insn_mode;
/* Implement FINAL_PRESCAN_INSN. This is used to emit bundles. */
void
-tilegx_final_prescan_insn (rtx insn)
+tilegx_final_prescan_insn (rtx_insn *insn)
{
/* Record this for tilegx_asm_output_opcode to examine. */
insn_mode = GET_MODE (insn);