Patchwork [9/16] powerpc: eoi xics ipi by hand in kexec

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Submitter Milton Miller
Date Oct. 10, 2008, 11:56 a.m.
Message ID <patch-xics-9@bga.com>
Download mbox | patch
Permalink /patch/3771/
State Accepted
Commit 1a57c926b6da56b4f904a0d8117ac362724f8c66
Headers show

Comments

Milton Miller - Oct. 10, 2008, 11:56 a.m.
EOI normally has the side effect of returning the cpu to the base
priority to recieve the next interrupt.  This is actually controlled
by the top byte of the xirr register.   When we are exiting the
kernel in kexec we must eoi the ipi for the next kernel because we
never return from the handler, but we want to leave interrupt
delivery blocked until the next kernel takes action.

Since the hardware ipi vector is fixed, its easiest to just do the
eoi explicitly.

Signed-off-by: Milton Miller <miltonm@bga.com>

Patch

Index: next.git/arch/powerpc/platforms/pseries/xics.c
===================================================================
--- next.git.orig/arch/powerpc/platforms/pseries/xics.c	2008-10-04 17:43:17.000000000 -0500
+++ next.git/arch/powerpc/platforms/pseries/xics.c	2008-10-04 21:56:17.000000000 -0500
@@ -757,25 +757,21 @@  void xics_teardown_cpu(void)
 
 void xics_kexec_teardown_cpu(int secondary)
 {
-	unsigned int ipi;
-	struct irq_desc *desc;
-
 	xics_teardown_cpu();
 
 	/*
-	 * we need to EOI the IPI
+	 * we take the ipi irq but and never return so we
+	 * need to EOI the IPI, but want to leave our priority 0
 	 *
-	 * probably need to check all the other interrupts too
+	 * should we check all the other interrupts too?
 	 * should we be flagging idle loop instead?
 	 * or creating some task to be scheduled?
 	 */
 
-	ipi = irq_find_mapping(xics_host, XICS_IPI);
-	if (ipi == XICS_IRQ_SPURIOUS)
-		return;
-	desc = get_irq_desc(ipi);
-	if (desc->chip && desc->chip->eoi)
-		desc->chip->eoi(ipi);
+	if (firmware_has_feature(FW_FEATURE_LPAR))
+		lpar_xirr_info_set((0x00 << 24) | XICS_IPI);
+	else
+		direct_xirr_info_set((0x00 << 24) | XICS_IPI);
 
 	/*
 	 * Some machines need to have at least one cpu in the GIQ,