@@ -59,7 +59,8 @@ struct mlx4_cq_context {
__be32 solicit_producer_index;
__be32 consumer_index;
__be32 producer_index;
- u32 reserved4[2];
+ __be32 pd; /* for sriov guest id */
+ u32 reserved4;
__be64 db_rec_addr;
};
@@ -293,6 +294,7 @@ int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt,
mtt_addr = mlx4_mtt_addr(dev, mtt);
cq_context->mtt_base_addr_h = mtt_addr >> 32;
cq_context->mtt_base_addr_l = cpu_to_be32(mtt_addr & 0xffffffff);
+ cq_context->pd = cpu_to_be32(dev->caps.pd_base << dev->caps.slave_pd_shift);
cq_context->db_rec_addr = cpu_to_be64(db_rec);
err = mlx4_SW2HW_CQ(dev, mailbox, cq->cqn);
@@ -486,9 +486,20 @@ static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
{
struct mlx4_priv *priv = mlx4_priv(dev);
int index;
+ int offset;
- index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
+ /* CX1: slave EQ DBs are located in the comm channel page */
+ if (mlx4_is_slave(dev) || mlx4_is_master(dev)) {
+ if (eq->eqn - dev->caps.reserved_eqs >= MLX4_MFUNC_EQ_NUM) {
+ mlx4_err(dev, "eqn:%d doorbell out of range (reserved:%d)\n",
+ eq->eqn, dev->caps.reserved_eqs);
+ return NULL;
+ }
+ offset = 0x800 + (eq->eqn - dev->caps.reserved_eqs) * 8;
+ return ((void *) priv->mfunc.comm) + offset;
+ }
+ index = eq->eqn / 4 - dev->caps.reserved_eqs / 4;
if (!priv->eq_table.uar_map[index]) {
priv->eq_table.uar_map[index] =
ioremap(pci_resource_start(dev->pdev, 2) +
@@ -45,7 +45,7 @@ int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn)
*pdn = mlx4_bitmap_alloc(&priv->pd_bitmap);
if (*pdn == -1)
return -ENOMEM;
-
+ *pdn |= dev->caps.pd_base << dev->caps.slave_pd_shift;
return 0;
}
EXPORT_SYMBOL_GPL(mlx4_pd_alloc);
@@ -72,12 +72,18 @@ void mlx4_cleanup_pd_table(struct mlx4_dev *dev)
int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar)
{
+ int offset;
+
uar->index = mlx4_bitmap_alloc(&mlx4_priv(dev)->uar_table.bitmap);
if (uar->index == -1)
return -ENOMEM;
- uar->pfn = (pci_resource_start(dev->pdev, 2) >> PAGE_SHIFT) + uar->index;
-
+ if (mlx4_is_slave(dev))
+ offset = uar->index % ((int) pci_resource_len(dev->pdev, 2) /
+ dev->caps.uar_page_size);
+ else
+ offset = uar->index;
+ uar->pfn = (pci_resource_start(dev->pdev, 2) >> PAGE_SHIFT) + offset;
return 0;
}
EXPORT_SYMBOL_GPL(mlx4_uar_alloc);
Resources are associated with functions by means of pds - the upper 7 msbs specify the function id. Since cqs do not refer to a specific pd, the function id is passed explicitly to hw in the cq context. For uars, which are statically partitioned between slaves, we only need to adjust their offsets with respect to the associated function bar. Signed-off-by: Liran Liss <liranl@mellanox.co.il> --- drivers/net/mlx4/cq.c | 4 +++- drivers/net/mlx4/eq.c | 13 ++++++++++++- drivers/net/mlx4/pd.c | 12 +++++++++--- 3 files changed, 24 insertions(+), 5 deletions(-)