From db96b2219b6752812cc4fecadef689fa90dc6f40 Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Tue, 29 Jul 2014 15:01:12 +0100
Subject: [PATCH 1/2] [AArch64][1/2] Fix offset error in loadwb* patterns.
---
gcc/config/aarch64/aarch64.c | 4 ++--
gcc/config/aarch64/aarch64.md | 18 ++++++++----------
2 files changed, 10 insertions(+), 12 deletions(-)
@@ -2006,10 +2006,10 @@ aarch64_gen_loadwb_pair (enum machine_mode mode, rtx base, rtx reg, rtx reg2,
{
case DImode:
return gen_loadwb_pairdi_di (base, base, reg, reg2, GEN_INT (adjustment),
- GEN_INT (adjustment + UNITS_PER_WORD));
+ GEN_INT (UNITS_PER_WORD));
case DFmode:
return gen_loadwb_pairdf_di (base, base, reg, reg2, GEN_INT (adjustment),
- GEN_INT (adjustment + UNITS_PER_WORD));
+ GEN_INT (UNITS_PER_WORD));
default:
gcc_unreachable ();
}
@@ -1016,20 +1016,19 @@
[(set_attr "type" "neon_store1_2reg<q>")]
)
-;; Load pair with writeback. This is primarily used in function epilogues
-;; when restoring [fp,lr]
+;; Load pair with post-index writeback. This is primarily used in function
+;; epilogues.
(define_insn "loadwb_pair<GPI:mode>_<P:mode>"
[(parallel
[(set (match_operand:P 0 "register_operand" "=k")
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "const_int_operand" "n")))
(set (match_operand:GPI 2 "register_operand" "=r")
- (mem:GPI (plus:P (match_dup 1)
- (match_dup 4))))
+ (mem:GPI (match_dup 1)))
(set (match_operand:GPI 3 "register_operand" "=r")
(mem:GPI (plus:P (match_dup 1)
(match_operand:P 5 "const_int_operand" "n"))))])]
- "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPI:MODE>mode)"
+ "INTVAL (operands[5]) == GET_MODE_SIZE (<GPI:MODE>mode)"
"ldp\\t%<w>2, %<w>3, [%1], %4"
[(set_attr "type" "load2")]
)
@@ -1040,18 +1039,17 @@
(plus:P (match_operand:P 1 "register_operand" "0")
(match_operand:P 4 "const_int_operand" "n")))
(set (match_operand:GPF 2 "register_operand" "=w")
- (mem:GPF (plus:P (match_dup 1)
- (match_dup 4))))
+ (mem:GPF (match_dup 1)))
(set (match_operand:GPF 3 "register_operand" "=w")
(mem:GPF (plus:P (match_dup 1)
(match_operand:P 5 "const_int_operand" "n"))))])]
- "INTVAL (operands[5]) == INTVAL (operands[4]) + GET_MODE_SIZE (<GPF:MODE>mode)"
+ "INTVAL (operands[5]) == GET_MODE_SIZE (<GPF:MODE>mode)"
"ldp\\t%<w>2, %<w>3, [%1], %4"
[(set_attr "type" "neon_load1_2reg")]
)
-;; Store pair with writeback. This is primarily used in function prologues
-;; when saving [fp,lr]
+;; Store pair with pre-index writeback. This is primarily used in function
+;; prologues.
(define_insn "storewb_pair<GPI:mode>_<P:mode>"
[(parallel
[(set (match_operand:P 0 "register_operand" "=&k")
--
1.8.3
on aarch64, we are using load register pair post-writeback instruction in epilogue. for example, for the following instruction: ldp, x0, x1, [sp], #16 what it's doing is: x0 <- MEM(sp + 0) x1 <- MEM(sp + 8) sp < sp + 16 while there is a glitch in our loadwb_pair* pattern, the restore of the first reg should always be with offset zero. (set (match_operand:GPI 2 "register_operand" "=r") - (mem:GPI (plus:P (match_dup 1) - (match_dup 4)))) + (mem:GPI (match_dup 1))) no regression on aarch64 bare-metal full test. ok to install ? gcc/ * config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Fix offset. (loadwb_pair<GPI:mode>_<P:mode>): Likewise. * config/aarch64/aarch64.c (aarch64_gen_loadwb_pair): Likewise.