[v5] pcie: Add Xilinx PCIe Host Bridge IP driver

This is the driver for Xilinx AXI PCIe Host Bridge Soft IP

Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
  xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
  xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
  xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
- Removed link_up bool flag from port structure, as it is not
  being used.
- Removed unused constants.
- Rebased on 3.16-rc6.
- Fixed some minor comments.
- Thanks Bjorn for the review.

Changes in v4:
- Regarding the comments to separate ECAM functionality,
  I have sent a separate patch and it is decided to implement
  it later. The patch is here,
  https://lkml.org/lkml/2014/5/18/54
- Fixed issue with adding configuration bus resource.
- Moved the logic for setting up bus resources to probe() from
  pcie_setup().
- Instead of mapping all the MSI interrupts in the probe, changed
  to map only when a MSI is requested.
- Earlier, the implementation of legacy and MSI interrupts init-
  is mutually exclusive, now changed to have the legacy interrupts
  init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
- Regarding the MSI generic implementation comment, I will plan to
  do on top of this driver patch.
- Rebased on 3.16-rc2.
- Fixed other minor comments.
- Thanks Arnd and Bjorn for the review.

Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as per the series
  "PCI: ARM: add support for generic PCI host controller"
- Modified devicetree binding documentation to update with interrupt-
  map properties.
- Use devm calls wherever applicable.
- Fixed minor comments from Jason
- Thanks Jason for the review and suggestions.

Changes in v2:
- Rebased on v3.14.0-rc8
- Removed IP specific DT properties like include-rc, axibar-num etc.,
  as suggested by Jason and Bjorn, Thanks
---
 .../devicetree/bindings/pci/xilinx-pcie.txt        |   62 ++
 drivers/pci/host/Kconfig                           |    7 +
 drivers/pci/host/Makefile                          |    1 +
 drivers/pci/host/pci-xilinx.c                      |  978 ++++++++++++++++++++
 4 files changed, 1048 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
 create mode 100644 drivers/pci/host/pci-xilinx.c

Hi Arnd and Rob,

I discussed with Bjorn and we believe this patch is in good shape to
apply.  And Bjorn requires ACKs to apply this patch.  So, could you
guys please review this patch and provided your ACKs to this patch.

Thanks
Srikanth

On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala <sthokal@xilinx.com> wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala <sthokal@xilinx.com>
> ---
> Changes in v5:
> - Removed unnecessary checking of port structure.
> - Changed the return type of verify_config from int to bool.
> - Renamed following functions,
>   xilinx_pcie_is_link_up() -> xilinx_pcie_link_is_up()
>   xilinx_pcie_verify_config() -> xilinx_pcie_valid_device()
>   xilinx_pcie_get_config_base() -> xilinx_pcie_config_base()
> - Removed link_up bool flag from port structure, as it is not
>   being used.
> - Removed unused constants.
> - Rebased on 3.16-rc6.
> - Fixed some minor comments.
> - Thanks Bjorn for the review.
>
> Changes in v4:
> - Regarding the comments to separate ECAM functionality,
>   I have sent a separate patch and it is decided to implement
>   it later. The patch is here,
>   https://lkml.org/lkml/2014/5/18/54
> - Fixed issue with adding configuration bus resource.
> - Moved the logic for setting up bus resources to probe() from
>   pcie_setup().
> - Instead of mapping all the MSI interrupts in the probe, changed
>   to map only when a MSI is requested.
> - Earlier, the implementation of legacy and MSI interrupts init-
>   is mutually exclusive, now changed to have the legacy interrupts
>   init always and MSI interrupt init based on CONFIG_PCI_MSI flag.
> - Regarding the MSI generic implementation comment, I will plan to
>   do on top of this driver patch.
> - Rebased on 3.16-rc2.
> - Fixed other minor comments.
> - Thanks Arnd and Bjorn for the review.
>
> Changes in v3:
> - Rebased on v3.15.0-rc1
> - Added support for interrupt-map DT functionality.
> - Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
> - Modified resource mapping logic as per the series
>   "PCI: ARM: add support for generic PCI host controller"
> - Modified devicetree binding documentation to update with interrupt-
>   map properties.
> - Use devm calls wherever applicable.
> - Fixed minor comments from Jason
> - Thanks Jason for the review and suggestions.
>
> Changes in v2:
> - Rebased on v3.14.0-rc8
> - Removed IP specific DT properties like include-rc, axibar-num etc.,
>   as suggested by Jason and Bjorn, Thanks
> ---
>  .../devicetree/bindings/pci/xilinx-pcie.txt        |   62 ++
>  drivers/pci/host/Kconfig                           |    7 +
>  drivers/pci/host/Makefile                          |    1 +
>  drivers/pci/host/pci-xilinx.c                      |  978 ++++++++++++++++++++
>  4 files changed, 1048 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/xilinx-pcie.txt
>  create mode 100644 drivers/pci/host/pci-xilinx.c
>
> diff --git a/Documentation/devicetree/bindings/pci/xilinx-pcie.txt b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> new file mode 100644
> index 0000000..3e2c88d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/xilinx-pcie.txt
> @@ -0,0 +1,62 @@
> +* Xilinx AXI PCIe Root Port Bridge DT description
> +
> +Required properties:
> +- #address-cells: Address representation for root ports, set to <3>
> +- #size-cells: Size representation for root ports, set to <2>
> +- #interrupt-cells: specifies the number of cells needed to encode an
> +       interrupt source. The value must be 1.
> +- compatible: Should contain "xlnx,axi-pcie-host-1.00.a"
> +- reg: Should contain AXI PCIe registers location and length
> +- device_type: must be "pci"
> +- interrupts: Should contain AXI PCIe interrupt
> +- interrupt-map-mask,
> +  interrupt-map: standard PCI properties to define the mapping of the
> +       PCI interface to interrupt numbers.
> +- ranges: ranges for the PCI memory regions (I/O space region is not
> +       supported by hardware)
> +       Please refer to the standard PCI bus binding document for a more
> +       detailed explanation
> +
> +Optional properties:
> +- bus-range: PCI bus numbers covered
> +
> +Interrupt controller child node
> ++++++++++++++++++++++++++++++++
> +Required properties:
> +- interrupt-controller: identifies the node as an interrupt controller
> +- #address-cells: specifies the number of cells needed to encode an
> +       address. The value must be 0.
> +- #interrupt-cells: specifies the number of cells needed to encode an
> +       interrupt source. The value must be 1.
> +
> +NOTE:
> +The core provides a single interrupt for both INTx/MSI messages. So,
> +created a interrupt controller node to support 'interrupt-map' DT
> +functionality.  The driver will create an IRQ domain for this map, decode
> +the four INTx interrupts in ISR and route them to this domain.
> +
> +
> +Example:
> +++++++++
> +
> +       pci_express: axi-pcie@50000000 {
> +               #address-cells = <3>;
> +               #size-cells = <2>;
> +               #interrupt-cells = <1>;
> +               compatible = "xlnx,axi-pcie-host-1.00.a";
> +               reg = < 0x50000000 0x10000000 >;
> +               device_type = "pci";
> +               interrupts = < 0 52 4 >;
> +               interrupt-map-mask = <0 0 0 7>;
> +               interrupt-map = <0 0 0 1 &pcie_intc 1>,
> +                               <0 0 0 2 &pcie_intc 2>,
> +                               <0 0 0 3 &pcie_intc 3>,
> +                               <0 0 0 4 &pcie_intc 4>;
> +               ranges = < 0x02000000 0 0x60000000 0x60000000 0 0x10000000 >;
> +
> +               pcie_intc: interrupt-controller {
> +                       interrupt-controller;
> +                       #address-cells = <0>;
> +                       #interrupt-cells = <1>;
> +               }
> +       };
> diff --git a/drivers/pci/host/Kconfig b/drivers/pci/host/Kconfig
> index 21df477..afedcde 100644
> --- a/drivers/pci/host/Kconfig
> +++ b/drivers/pci/host/Kconfig
> @@ -46,4 +46,11 @@ config PCI_HOST_GENERIC
>           Say Y here if you want to support a simple generic PCI host
>           controller, such as the one emulated by kvmtool.
>
> +config PCI_XILINX
> +       bool "Xilinx AXI PCIe host bridge support"
> +       depends on ARCH_ZYNQ
> +       help
> +         Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
> +         Host Bridge driver.
> +
>  endmenu
> diff --git a/drivers/pci/host/Makefile b/drivers/pci/host/Makefile
> index 611ba4b..68dfd06 100644
> --- a/drivers/pci/host/Makefile
> +++ b/drivers/pci/host/Makefile
> @@ -6,3 +6,4 @@ obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o
>  obj-$(CONFIG_PCI_RCAR_GEN2) += pci-rcar-gen2.o
>  obj-$(CONFIG_PCI_RCAR_GEN2_PCIE) += pcie-rcar.o
>  obj-$(CONFIG_PCI_HOST_GENERIC) += pci-host-generic.o
> +obj-$(CONFIG_PCI_XILINX) += pci-xilinx.o
> diff --git a/drivers/pci/host/pci-xilinx.c b/drivers/pci/host/pci-xilinx.c
> new file mode 100644
> index 0000000..5dd9fda
> --- /dev/null
> +++ b/drivers/pci/host/pci-xilinx.c
> @@ -0,0 +1,978 @@
> +/*
> + * PCIe host controller driver for Xilinx AXI PCIe Bridge
> + *
> + * Copyright (c) 2012 - 2014 Xilinx, Inc.
> + *
> + * Based on the Tegra PCIe driver
> + *
> + * Bits taken from Synopsys Designware Host controller driver and
> + * ARM PCI Host generic driver.
> + *
> + * This program is free software: you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation, either version 2 of the License, or
> + * (at your option) any later version.
> + */
> +
> +#include <linux/interrupt.h>
> +#include <linux/irq.h>
> +#include <linux/irqdomain.h>
> +#include <linux/kernel.h>
> +#include <linux/module.h>
> +#include <linux/msi.h>
> +#include <linux/of_address.h>
> +#include <linux/of_pci.h>
> +#include <linux/of_platform.h>
> +#include <linux/of_irq.h>
> +#include <linux/pci.h>
> +#include <linux/platform_device.h>
> +
> +/* Register definitions */
> +#define XILINX_PCIE_REG_BIR            0x00000130
> +#define XILINX_PCIE_REG_IDR            0x00000138
> +#define XILINX_PCIE_REG_IMR            0x0000013c
> +#define XILINX_PCIE_REG_PSCR           0x00000144
> +#define XILINX_PCIE_REG_RPSC           0x00000148
> +#define XILINX_PCIE_REG_MSIBASE1       0x0000014c
> +#define XILINX_PCIE_REG_MSIBASE2       0x00000150
> +#define XILINX_PCIE_REG_RPEFR          0x00000154
> +#define XILINX_PCIE_REG_RPIFR1         0x00000158
> +#define XILINX_PCIE_REG_RPIFR2         0x0000015c
> +
> +/* Interrupt registers definitions */
> +#define XILINX_PCIE_INTR_LINK_DOWN     BIT(0)
> +#define XILINX_PCIE_INTR_ECRC_ERR      BIT(1)
> +#define XILINX_PCIE_INTR_STR_ERR       BIT(2)
> +#define XILINX_PCIE_INTR_HOT_RESET     BIT(3)
> +#define XILINX_PCIE_INTR_CFG_TIMEOUT   BIT(8)
> +#define XILINX_PCIE_INTR_CORRECTABLE   BIT(9)
> +#define XILINX_PCIE_INTR_NONFATAL      BIT(10)
> +#define XILINX_PCIE_INTR_FATAL         BIT(11)
> +#define XILINX_PCIE_INTR_INTX          BIT(16)
> +#define XILINX_PCIE_INTR_MSI           BIT(17)
> +#define XILINX_PCIE_INTR_SLV_UNSUPP    BIT(20)
> +#define XILINX_PCIE_INTR_SLV_UNEXP     BIT(21)
> +#define XILINX_PCIE_INTR_SLV_COMPL     BIT(22)
> +#define XILINX_PCIE_INTR_SLV_ERRP      BIT(23)
> +#define XILINX_PCIE_INTR_SLV_CMPABT    BIT(24)
> +#define XILINX_PCIE_INTR_SLV_ILLBUR    BIT(25)
> +#define XILINX_PCIE_INTR_MST_DECERR    BIT(26)
> +#define XILINX_PCIE_INTR_MST_SLVERR    BIT(27)
> +#define XILINX_PCIE_INTR_MST_ERRP      BIT(28)
> +#define XILINX_PCIE_IMR_ALL_MASK       0x1FF30FED
> +#define XILINX_PCIE_IDR_ALL_MASK       0xFFFFFFFF
> +
> +/* Root Port Error FIFO Read Register definitions */
> +#define XILINX_PCIE_RPEFR_ERR_VALID    BIT(18)
> +#define XILINX_PCIE_RPEFR_REQ_ID       GENMASK(15, 0)
> +#define XILINX_PCIE_RPEFR_ALL_MASK     0xFFFFFFFF
> +
> +/* Root Port Interrupt FIFO Read Register 1 definitions */
> +#define XILINX_PCIE_RPIFR1_INTR_VALID  BIT(31)
> +#define XILINX_PCIE_RPIFR1_MSI_INTR    BIT(30)
> +#define XILINX_PCIE_RPIFR1_INTR_MASK   GENMASK(28, 27)
> +#define XILINX_PCIE_RPIFR1_ALL_MASK    0xFFFFFFFF
> +#define XILINX_PCIE_RPIFR1_INTR_SHIFT          27
> +
> +/* Bridge Info Register definitions */
> +#define XILINX_PCIE_BIR_ECAM_SZ_MASK   GENMASK(18, 16)
> +#define XILINX_PCIE_BIR_ECAM_SZ_SHIFT  16
> +
> +/* Root Port Interrupt FIFO Read Register 2 definitions */
> +#define XILINX_PCIE_RPIFR2_MSG_DATA    GENMASK(15, 0)
> +
> +/* Root Port Status/control Register definitions */
> +#define XILINX_PCIE_REG_RPSC_BEN       BIT(0)
> +
> +/* Phy Status/Control Register definitions */
> +#define XILINX_PCIE_REG_PSCR_LNKUP     BIT(11)
> +
> +/* ECAM definitions */
> +#define ECAM_BUS_NUM_SHIFT             20
> +#define ECAM_DEV_NUM_SHIFT             12
> +
> +/* Number of MSI IRQs */
> +#define XILINX_NUM_MSI_IRQS            128
> +
> +/* Number of Memory Resources */
> +#define XILINX_MAX_NUM_RESOURCES       3
> +
> +/**
> + * struct xilinx_pcie_port - PCIe port information
> + * @reg_base: IO Mapped Register Base
> + * @irq: Interrupt number
> + * @msi_pages: MSI pages
> + * @root_busno: Root Bus number
> + * @dev: Device pointer
> + * @irq_domain: IRQ domain pointer
> + * @bus_range: Bus range
> + * @resources: Bus Resources
> + */
> +struct xilinx_pcie_port {
> +       void __iomem *reg_base;
> +       u32 irq;
> +       unsigned long msi_pages;
> +       u8 root_busno;
> +       struct device *dev;
> +       struct irq_domain *irq_domain;
> +       struct resource bus_range;
> +       struct list_head resources;
> +};
> +
> +static DECLARE_BITMAP(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
> +
> +static inline struct xilinx_pcie_port *sys_to_pcie(struct pci_sys_data *sys)
> +{
> +       return sys->private_data;
> +}
> +
> +static inline u32 pcie_read(struct xilinx_pcie_port *port, u32 reg)
> +{
> +       return readl(port->reg_base + reg);
> +}
> +
> +static inline void pcie_write(struct xilinx_pcie_port *port,
> +                             u32 val, u32 reg)
> +{
> +       writel(val, port->reg_base + reg);
> +}
> +
> +static inline bool xilinx_pcie_link_is_up(struct xilinx_pcie_port *port)
> +{
> +       return (pcie_read(port, XILINX_PCIE_REG_PSCR) &
> +               XILINX_PCIE_REG_PSCR_LNKUP) ? 1 : 0;
> +}
> +
> +/**
> + * xilinx_pcie_clear_err_interrupts - Clear Error Interrupts
> + * @port: PCIe port information
> + */
> +static void xilinx_pcie_clear_err_interrupts(struct xilinx_pcie_port *port)
> +{
> +       u32 val = pcie_read(port, XILINX_PCIE_REG_RPEFR);
> +
> +       if (val & XILINX_PCIE_RPEFR_ERR_VALID) {
> +               dev_dbg(port->dev, "Requester ID %d\n",
> +                       val & XILINX_PCIE_RPEFR_REQ_ID);
> +               pcie_write(port, XILINX_PCIE_RPEFR_ALL_MASK,
> +                          XILINX_PCIE_REG_RPEFR);
> +       }
> +}
> +
> +/**
> + * xilinx_pcie_valid_device - Check if a valid device is present on bus
> + * @bus: PCI Bus structure
> + * @devfn: device/function
> + *
> + * Return: 'true' on success and 'false' if invalid device is found
> + */
> +static bool xilinx_pcie_valid_device(struct pci_bus *bus,
> +                                    unsigned int devfn)
> +{
> +       struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
> +
> +       /* Check if link is up when trying to access downstream ports */
> +       if (bus->number != port->root_busno)
> +               if (!xilinx_pcie_link_is_up(port))
> +                       return false;
> +
> +       /* Only one device down on each root port */
> +       if (bus->number == port->root_busno && devfn > 0)
> +               return false;
> +
> +       /*
> +        * Do not read more than one device on the bus directly attached
> +        * to RC.
> +        */
> +       if (bus->primary == port->root_busno && devfn > 0)
> +               return false;
> +
> +       return true;
> +}
> +
> +/**
> + * xilinx_pcie_config_base - Get configuration base
> + * @bus: PCI Bus structure
> + * @devfn: Device/function
> + * @where: Offset from base
> + *
> + * Return: Base address of the configuration space needed to be
> + *        accessed.
> + */
> +static void __iomem *xilinx_pcie_config_base(struct pci_bus *bus,
> +                                                unsigned int devfn,
> +                                                int where)
> +{
> +       struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
> +       int relbus;
> +
> +       relbus = (bus->number << ECAM_BUS_NUM_SHIFT) |
> +                (devfn << ECAM_DEV_NUM_SHIFT);
> +
> +       return port->reg_base + relbus + where;
> +}
> +
> +/**
> + * xilinx_pcie_read_config - Read configuration space
> + * @bus: PCI Bus structure
> + * @devfn: Device/function
> + * @where: Offset from base
> + * @size: Byte/word/dword
> + * @val: Value to be read
> + *
> + * Return: PCIBIOS_SUCCESSFUL on success
> + *        EINVAL/PCIBIOS_DEVICE_NOT_FOUND/PCIBIOS_BAD_REGISTER_NUMBER
> + *        on failure.
> + */
> +static int xilinx_pcie_read_config(struct pci_bus *bus,
> +                                  unsigned int devfn, int where,
> +                                  int size, u32 *val)
> +{
> +       void __iomem *addr;
> +
> +       if (!xilinx_pcie_valid_device(bus, devfn)) {
> +               *val = 0xFFFFFFFF;
> +               return PCIBIOS_DEVICE_NOT_FOUND;
> +       }
> +
> +       addr = xilinx_pcie_config_base(bus, devfn, where);
> +
> +       switch (size) {
> +       case 1:
> +               *val = readb(addr);
> +               break;
> +       case 2:
> +               *val = readw(addr);
> +               break;
> +       default:
> +               *val = readl(addr);
> +               break;
> +       }
> +
> +       return PCIBIOS_SUCCESSFUL;
> +}
> +
> +/**
> + * xilinx_pcie_write_config - Write configuration space
> + * @bus: PCI Bus structure
> + * @devfn: Device/function
> + * @where: Offset from base
> + * @size: Byte/word/dword
> + * @val: Value to be written to device
> + *
> + * Return: PCIBIOS_SUCCESSFUL on success,
> + *        EINVAL/PCIBIOS_DEVICE_NOT_FOUND/PCIBIOS_BAD_REGISTER_NUMBER
> + *        on failure.
> + */
> +static int xilinx_pcie_write_config(struct pci_bus *bus,
> +                                   unsigned int devfn, int where,
> +                                   int size, u32 val)
> +{
> +       void __iomem *addr;
> +
> +       if (!xilinx_pcie_valid_device(bus, devfn))
> +               return PCIBIOS_DEVICE_NOT_FOUND;
> +
> +       addr = xilinx_pcie_config_base(bus, devfn, where);
> +
> +       switch (size) {
> +       case 1:
> +               writeb(val, addr);
> +               break;
> +       case 2:
> +               writew(val, addr);
> +               break;
> +       default:
> +               writel(val, addr);
> +               break;
> +       }
> +
> +       return PCIBIOS_SUCCESSFUL;
> +}
> +
> +/* PCIe operations */
> +static struct pci_ops xilinx_pcie_ops = {
> +       .read  = xilinx_pcie_read_config,
> +       .write = xilinx_pcie_write_config,
> +};
> +
> +/* MSI functions */
> +
> +/**
> + * xilinx_pcie_destroy_msi - Free MSI number
> + * @irq: IRQ to be freed
> + */
> +static void xilinx_pcie_destroy_msi(unsigned int irq)
> +{
> +       struct irq_desc *desc;
> +       struct msi_desc *msi;
> +       struct xilinx_pcie_port *port;
> +
> +       desc = irq_to_desc(irq);
> +       msi = irq_desc_get_msi_desc(desc);
> +       port = sys_to_pcie(msi->dev->bus->sysdata);
> +
> +       if (!test_bit(irq, msi_irq_in_use))
> +               dev_err(port->dev, "Trying to free unused MSI#%d\n", irq);
> +       else
> +               clear_bit(irq, msi_irq_in_use);
> +}
> +
> +/**
> + * xilinx_pcie_assign_msi - Allocate MSI number
> + * @port: PCIe port structure
> + *
> + * Return: A valid IRQ on success and error value on failure.
> + */
> +static int xilinx_pcie_assign_msi(struct xilinx_pcie_port *port)
> +{
> +       int pos;
> +
> +       pos = find_first_zero_bit(msi_irq_in_use, XILINX_NUM_MSI_IRQS);
> +       if (pos < XILINX_NUM_MSI_IRQS)
> +               set_bit(pos, msi_irq_in_use);
> +       else
> +               return -ENOSPC;
> +
> +       return pos;
> +}
> +
> +/**
> + * xilinx_msi_teardown_irq - Destroy the MSI
> + * @chip: MSI Chip descriptor
> + * @irq: MSI IRQ to destroy
> + */
> +static void xilinx_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
> +{
> +       xilinx_pcie_destroy_msi(irq);
> +}
> +
> +/**
> + * xilinx_pcie_msi_setup_irq - Setup MSI request
> + * @chip: MSI chip pointer
> + * @pdev: PCIe device pointer
> + * @desc: MSI descriptor pointer
> + *
> + * Return: '0' on success and error value on failure
> + */
> +static int xilinx_pcie_msi_setup_irq(struct msi_chip *chip,
> +                                    struct pci_dev *pdev,
> +                                    struct msi_desc *desc)
> +{
> +       struct xilinx_pcie_port *port = sys_to_pcie(pdev->bus->sysdata);
> +       unsigned int irq;
> +       int hwirq;
> +       struct msi_msg msg;
> +       phys_addr_t msg_addr;
> +
> +       hwirq = xilinx_pcie_assign_msi(port);
> +       if (irq < 0)
> +               return irq;
> +
> +       irq = irq_create_mapping(port->irq_domain, hwirq);
> +       if (!irq)
> +               return -EINVAL;
> +
> +       irq_set_msi_desc(irq, desc);
> +
> +       msg_addr = virt_to_phys((void *)port->msi_pages);
> +
> +       msg.address_hi = 0;
> +       msg.address_lo = msg_addr;
> +       msg.data = irq;
> +
> +       write_msi_msg(irq, &msg);
> +
> +       return 0;
> +}
> +
> +/* MSI Chip Descriptor */
> +static struct msi_chip xilinx_pcie_msi_chip = {
> +       .setup_irq = xilinx_pcie_msi_setup_irq,
> +       .teardown_irq = xilinx_msi_teardown_irq,
> +};
> +
> +/* HW Interrupt Chip Descriptor */
> +static struct irq_chip xilinx_msi_irq_chip = {
> +       .name = "Xilinx PCIe MSI",
> +       .irq_enable = unmask_msi_irq,
> +       .irq_disable = mask_msi_irq,
> +       .irq_mask = mask_msi_irq,
> +       .irq_unmask = unmask_msi_irq,
> +};
> +
> +/**
> + * xilinx_pcie_msi_map - Set the handler for the MSI and mark IRQ as valid
> + * @domain: IRQ domain
> + * @irq: Virtual IRQ number
> + * @hwirq: HW interrupt number
> + *
> + * Return: Always returns 0.
> + */
> +static int xilinx_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
> +                              irq_hw_number_t hwirq)
> +{
> +       irq_set_chip_and_handler(irq, &xilinx_msi_irq_chip, handle_simple_irq);
> +       irq_set_chip_data(irq, domain->host_data);
> +       set_irq_flags(irq, IRQF_VALID);
> +
> +       return 0;
> +}
> +
> +/* IRQ Domain operations */
> +static const struct irq_domain_ops msi_domain_ops = {
> +       .map = xilinx_pcie_msi_map,
> +};
> +
> +/**
> + * xilinx_pcie_enable_msi - Enable MSI support
> + * @port: PCIe port information
> + */
> +static void xilinx_pcie_enable_msi(struct xilinx_pcie_port *port)
> +{
> +       phys_addr_t msg_addr;
> +
> +       port->msi_pages = __get_free_pages(GFP_KERNEL, 0);
> +       msg_addr = virt_to_phys((void *)port->msi_pages);
> +       pcie_write(port, 0x0, XILINX_PCIE_REG_MSIBASE1);
> +       pcie_write(port, msg_addr, XILINX_PCIE_REG_MSIBASE2);
> +}
> +
> +/**
> + * xilinx_pcie_add_bus - Add MSI chip info to PCIe bus
> + * @bus: PCIe bus
> + */
> +static void xilinx_pcie_add_bus(struct pci_bus *bus)
> +{
> +       if (IS_ENABLED(CONFIG_PCI_MSI)) {
> +               struct xilinx_pcie_port *port = sys_to_pcie(bus->sysdata);
> +
> +               xilinx_pcie_msi_chip.dev = port->dev;
> +               bus->msi = &xilinx_pcie_msi_chip;
> +       }
> +}
> +
> +/* INTx Functions */
> +
> +/**
> + * xilinx_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
> + * @domain: IRQ domain
> + * @irq: Virtual IRQ number
> + * @hwirq: HW interrupt number
> + *
> + * Return: Always returns 0.
> + */
> +static int xilinx_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
> +                               irq_hw_number_t hwirq)
> +{
> +       irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
> +       irq_set_chip_data(irq, domain->host_data);
> +       set_irq_flags(irq, IRQF_VALID);
> +
> +       return 0;
> +}
> +
> +/* INTx IRQ Domain operations */
> +static const struct irq_domain_ops intx_domain_ops = {
> +       .map = xilinx_pcie_intx_map,
> +};
> +
> +/* PCIe HW Functions */
> +
> +/**
> + * xilinx_pcie_intr_handler - Interrupt Service Handler
> + * @irq: IRQ number
> + * @data: PCIe port information
> + *
> + * Return: IRQ_HANDLED on success and IRQ_NONE on failure
> + */
> +static irqreturn_t xilinx_pcie_intr_handler(int irq, void *data)
> +{
> +       struct xilinx_pcie_port *port = (struct xilinx_pcie_port *)data;
> +       u32 val, mask, status, msi_data;
> +
> +       /* Read interrupt decode and mask registers */
> +       val = pcie_read(port, XILINX_PCIE_REG_IDR);
> +       mask = pcie_read(port, XILINX_PCIE_REG_IMR);
> +
> +       status = val & mask;
> +       if (!status)
> +               return IRQ_NONE;
> +
> +       if (status & XILINX_PCIE_INTR_LINK_DOWN)
> +               dev_warn(port->dev, "Link Down\n");
> +
> +       if (status & XILINX_PCIE_INTR_ECRC_ERR)
> +               dev_warn(port->dev, "ECRC failed\n");
> +
> +       if (status & XILINX_PCIE_INTR_STR_ERR)
> +               dev_warn(port->dev, "Streaming error\n");
> +
> +       if (status & XILINX_PCIE_INTR_HOT_RESET)
> +               dev_info(port->dev, "Hot reset\n");
> +
> +       if (status & XILINX_PCIE_INTR_CFG_TIMEOUT)
> +               dev_warn(port->dev, "ECAM access timeout\n");
> +
> +       if (status & XILINX_PCIE_INTR_CORRECTABLE) {
> +               dev_warn(port->dev, "Correctable error message\n");
> +               xilinx_pcie_clear_err_interrupts(port);
> +       }
> +
> +       if (status & XILINX_PCIE_INTR_NONFATAL) {
> +               dev_warn(port->dev, "Non fatal error message\n");
> +               xilinx_pcie_clear_err_interrupts(port);
> +       }
> +
> +       if (status & XILINX_PCIE_INTR_FATAL) {
> +               dev_warn(port->dev, "Fatal error message\n");
> +               xilinx_pcie_clear_err_interrupts(port);
> +       }
> +
> +       if (status & XILINX_PCIE_INTR_INTX) {
> +               /* INTx interrupt received */
> +               val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
> +
> +               /* Check whether interrupt valid */
> +               if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
> +                       dev_warn(port->dev, "RP Intr FIFO1 read error\n");
> +                       return IRQ_HANDLED;
> +               }
> +
> +               /* Clear interrupt FIFO register 1 */
> +               pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
> +                          XILINX_PCIE_REG_RPIFR1);
> +
> +               /* Handle INTx Interrupt */
> +               val = ((val & XILINX_PCIE_RPIFR1_INTR_MASK) >>
> +                       XILINX_PCIE_RPIFR1_INTR_SHIFT) + 1;
> +               generic_handle_irq(irq_find_mapping(port->irq_domain, val));
> +       }
> +
> +       if (status & XILINX_PCIE_INTR_MSI) {
> +               /* MSI Interrupt */
> +               val = pcie_read(port, XILINX_PCIE_REG_RPIFR1);
> +
> +               if (!(val & XILINX_PCIE_RPIFR1_INTR_VALID)) {
> +                       dev_warn(port->dev, "RP Intr FIFO1 read error\n");
> +                       return IRQ_HANDLED;
> +               }
> +
> +               if (val & XILINX_PCIE_RPIFR1_MSI_INTR) {
> +                       msi_data = pcie_read(port, XILINX_PCIE_REG_RPIFR2) &
> +                                  XILINX_PCIE_RPIFR2_MSG_DATA;
> +
> +                       /* Clear interrupt FIFO register 1 */
> +                       pcie_write(port, XILINX_PCIE_RPIFR1_ALL_MASK,
> +                                  XILINX_PCIE_REG_RPIFR1);
> +
> +                       if (IS_ENABLED(CONFIG_PCI_MSI)) {
> +                               /* Handle MSI Interrupt */
> +                               generic_handle_irq(msi_data);
> +                       }
> +               }
> +       }
> +
> +       if (status & XILINX_PCIE_INTR_SLV_UNSUPP)
> +               dev_warn(port->dev, "Slave unsupported request\n");
> +
> +       if (status & XILINX_PCIE_INTR_SLV_UNEXP)
> +               dev_warn(port->dev, "Slave unexpected completion\n");
> +
> +       if (status & XILINX_PCIE_INTR_SLV_COMPL)
> +               dev_warn(port->dev, "Slave completion timeout\n");
> +
> +       if (status & XILINX_PCIE_INTR_SLV_ERRP)
> +               dev_warn(port->dev, "Slave Error Poison\n");
> +
> +       if (status & XILINX_PCIE_INTR_SLV_CMPABT)
> +               dev_warn(port->dev, "Slave Completer Abort\n");
> +
> +       if (status & XILINX_PCIE_INTR_SLV_ILLBUR)
> +               dev_warn(port->dev, "Slave Illegal Burst\n");
> +
> +       if (status & XILINX_PCIE_INTR_MST_DECERR)
> +               dev_warn(port->dev, "Master decode error\n");
> +
> +       if (status & XILINX_PCIE_INTR_MST_SLVERR)
> +               dev_warn(port->dev, "Master slave error\n");
> +
> +       if (status & XILINX_PCIE_INTR_MST_ERRP)
> +               dev_warn(port->dev, "Master error poison\n");
> +
> +       /* Clear the Interrupt Decode register */
> +       pcie_write(port, status, XILINX_PCIE_REG_IDR);
> +
> +       return IRQ_HANDLED;
> +}
> +
> +/**
> + * xilinx_pcie_free_irq_domain - Free IRQ domain
> + * @port: PCIe port information
> + */
> +static void xilinx_pcie_free_irq_domain(struct xilinx_pcie_port *port)
> +{
> +       int i;
> +       u32 irq, num_irqs;
> +
> +       /* Free IRQ Domain */
> +       if (IS_ENABLED(CONFIG_PCI_MSI)) {
> +
> +               free_pages(port->msi_pages, 0);
> +
> +               num_irqs = XILINX_NUM_MSI_IRQS;
> +       } else {
> +               /* INTx */
> +               num_irqs = 4;
> +       }
> +
> +       for (i = 0; i < num_irqs; i++) {
> +               irq = irq_find_mapping(port->irq_domain, i);
> +               if (irq > 0)
> +                       irq_dispose_mapping(irq);
> +       }
> +
> +       irq_domain_remove(port->irq_domain);
> +}
> +
> +/**
> + * xilinx_pcie_init_irq_domain - Initialize IRQ domain
> + * @port: PCIe port information
> + *
> + * Return: '0' on success and error value on failure
> + */
> +static int xilinx_pcie_init_irq_domain(struct xilinx_pcie_port *port)
> +{
> +       struct device *dev = port->dev;
> +       struct device_node *node = dev->of_node;
> +       struct device_node *pcie_intc_node;
> +
> +       /* Setup INTx */
> +       pcie_intc_node = of_get_next_child(node, NULL);
> +       if (!pcie_intc_node) {
> +               dev_err(dev, "No PCIe Intc node found\n");
> +               return PTR_ERR(pcie_intc_node);
> +       }
> +
> +       port->irq_domain = irq_domain_add_linear(pcie_intc_node, 4,
> +                                                &intx_domain_ops,
> +                                                port);
> +       if (!port->irq_domain) {
> +               dev_err(dev, "Failed to get a INTx IRQ domain\n");
> +               return PTR_ERR(port->irq_domain);
> +       }
> +
> +       /* Setup MSI */
> +       if (IS_ENABLED(CONFIG_PCI_MSI)) {
> +               port->irq_domain = irq_domain_add_linear(node,
> +                                                        XILINX_NUM_MSI_IRQS,
> +                                                        &msi_domain_ops,
> +                                                        &xilinx_pcie_msi_chip);
> +               if (!port->irq_domain) {
> +                       dev_err(dev, "Failed to get a MSI IRQ domain\n");
> +                       return PTR_ERR(port->irq_domain);
> +               }
> +
> +               xilinx_pcie_enable_msi(port);
> +       }
> +
> +       return 0;
> +}
> +
> +/**
> + * xilinx_pcie_init_port - Initialize hardware
> + * @port: PCIe port information
> + */
> +static void xilinx_pcie_init_port(struct xilinx_pcie_port *port)
> +{
> +       if (xilinx_pcie_link_is_up(port))
> +               dev_info(port->dev, "PCIe Link is UP\n");
> +       else
> +               dev_info(port->dev, "PCIe Link is DOWN\n");
> +
> +       /* Disable all interrupts */
> +       pcie_write(port, ~XILINX_PCIE_IDR_ALL_MASK,
> +                  XILINX_PCIE_REG_IMR);
> +
> +       /* Clear pending interrupts */
> +       pcie_write(port, pcie_read(port, XILINX_PCIE_REG_IDR) &
> +                        XILINX_PCIE_IMR_ALL_MASK,
> +                  XILINX_PCIE_REG_IDR);
> +
> +       /* Enable all interrupts */
> +       pcie_write(port, XILINX_PCIE_IMR_ALL_MASK, XILINX_PCIE_REG_IMR);
> +
> +       /* Enable the Bridge enable bit */
> +       pcie_write(port, pcie_read(port, XILINX_PCIE_REG_RPSC) |
> +                        XILINX_PCIE_REG_RPSC_BEN,
> +                  XILINX_PCIE_REG_RPSC);
> +}
> +
> +/**
> + * xilinx_pcie_setup - Setup memory resources
> + * @nr: Bus number
> + * @sys: Per controller structure
> + *
> + * Return: '1' on success and error value on failure
> + */
> +static int xilinx_pcie_setup(int nr, struct pci_sys_data *sys)
> +{
> +       struct xilinx_pcie_port *port = sys_to_pcie(sys);
> +
> +       list_splice_init(&port->resources, &sys->resources);
> +
> +       return 1;
> +}
> +
> +/**
> + * xilinx_pcie_scan_bus - Scan PCIe bus for devices
> + * @nr: Bus number
> + * @sys: Per controller structure
> + *
> + * Return: Valid Bus pointer on success and NULL on failure
> + */
> +static struct pci_bus __init *xilinx_pcie_scan_bus(int nr,
> +                                                  struct pci_sys_data *sys)
> +{
> +       struct xilinx_pcie_port *port = sys_to_pcie(sys);
> +       struct pci_bus *bus;
> +
> +       port->root_busno = sys->busnr;
> +       bus = pci_scan_root_bus(port->dev, sys->busnr, &xilinx_pcie_ops,
> +                               sys, &sys->resources);
> +
> +       return bus;
> +}
> +
> +/**
> + * xilinx_pcie_parse_and_add_res - Add resources by parsing ranges
> + * @port: PCIe port information
> + *
> + * Return: '0' on success and error value on failure
> + */
> +static int xilinx_pcie_parse_and_add_res(struct xilinx_pcie_port *port)
> +{
> +       struct device *dev = port->dev;
> +       struct device_node *node = dev->of_node;
> +       struct resource *mem;
> +       resource_size_t offset;
> +       struct of_pci_range_parser parser;
> +       struct of_pci_range range;
> +       struct pci_host_bridge_window *win;
> +       int err = 0, mem_resno = 0;
> +
> +       /* Get the ranges */
> +       if (of_pci_range_parser_init(&parser, node)) {
> +               dev_err(dev, "missing \"ranges\" property\n");
> +               return -EINVAL;
> +       }
> +
> +       /* Parse the ranges and add the resources found to the list */
> +       for_each_of_pci_range(&parser, &range) {
> +
> +               if (mem_resno >= XILINX_MAX_NUM_RESOURCES) {
> +                       dev_err(dev, "Maximum memory resources exceeded\n");
> +                       return -EINVAL;
> +               }
> +
> +               mem = devm_kmalloc(dev, sizeof(*mem), GFP_KERNEL);
> +               if (!mem) {
> +                       err = -ENOMEM;
> +                       goto free_resources;
> +               }
> +
> +               of_pci_range_to_resource(&range, node, mem);
> +
> +               switch (mem->flags & IORESOURCE_TYPE_BITS) {
> +               case IORESOURCE_MEM:
> +                       offset = range.cpu_addr - range.pci_addr;
> +                       mem_resno++;
> +                       break;
> +               default:
> +                       err = -EINVAL;
> +                       break;
> +               }
> +
> +               if (err < 0) {
> +                       dev_warn(dev, "Invalid resource found %pR\n", mem);
> +                       continue;
> +               }
> +
> +               err = request_resource(&iomem_resource, mem);
> +               if (err)
> +                       goto free_resources;
> +
> +               pci_add_resource_offset(&port->resources, mem, offset);
> +       }
> +
> +       /* Get the bus range */
> +       if (of_pci_parse_bus_range(node, &port->bus_range)) {
> +               u32 val = pcie_read(port, XILINX_PCIE_REG_BIR);
> +               u8 last;
> +
> +               last = (val & XILINX_PCIE_BIR_ECAM_SZ_MASK) >>
> +                       XILINX_PCIE_BIR_ECAM_SZ_SHIFT;
> +
> +               port->bus_range = (struct resource) {
> +                       .name   = node->name,
> +                       .start  = 0,
> +                       .end    = last,
> +                       .flags  = IORESOURCE_BUS,
> +               };
> +       }
> +
> +       /* Register bus resource */
> +       pci_add_resource(&port->resources, &port->bus_range);
> +
> +       return 0;
> +
> +free_resources:
> +       release_child_resources(&iomem_resource);
> +       list_for_each_entry(win, &port->resources, list)
> +               devm_kfree(dev, win->res);
> +       pci_free_resource_list(&port->resources);
> +
> +       return err;
> +}
> +
> +/**
> + * xilinx_pcie_parse_dt - Parse Device tree
> + * @port: PCIe port information
> + *
> + * Return: '0' on success and error value on failure
> + */
> +static int xilinx_pcie_parse_dt(struct xilinx_pcie_port *port)
> +{
> +       struct device *dev = port->dev;
> +       struct device_node *node = dev->of_node;
> +       struct resource regs;
> +       const char *type;
> +       int err;
> +
> +       type = of_get_property(node, "device_type", NULL);
> +       if (!type || strcmp(type, "pci")) {
> +               dev_err(dev, "invalid \"device_type\" %s\n", type);
> +               return -EINVAL;
> +       }
> +
> +       err = of_address_to_resource(node, 0, &regs);
> +       if (err) {
> +               dev_err(dev, "missing \"reg\" property\n");
> +               return err;
> +       }
> +
> +       port->reg_base = devm_ioremap_resource(dev, &regs);
> +       if (IS_ERR(port->reg_base))
> +               return PTR_ERR(port->reg_base);
> +
> +       port->irq = irq_of_parse_and_map(node, 0);
> +       err = devm_request_irq(dev, port->irq, xilinx_pcie_intr_handler,
> +                              IRQF_SHARED, "xilinx-pcie", port);
> +       if (err) {
> +               dev_err(dev, "unable to request irq %d\n", port->irq);
> +               return err;
> +       }
> +
> +       return 0;
> +}
> +
> +/**
> + * xilinx_pcie_probe - Probe function
> + * @pdev: Platform device pointer
> + *
> + * Return: '0' on success and error value on failure
> + */
> +static int xilinx_pcie_probe(struct platform_device *pdev)
> +{
> +       struct xilinx_pcie_port *port;
> +       struct hw_pci hw;
> +       struct device *dev = &pdev->dev;
> +       int err;
> +
> +       if (!dev->of_node)
> +               return -ENODEV;
> +
> +       port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
> +       if (!port)
> +               return -ENOMEM;
> +
> +       port->dev = dev;
> +
> +       err = xilinx_pcie_parse_dt(port);
> +       if (err) {
> +               dev_err(dev, "Parsing DT failed\n");
> +               return err;
> +       }
> +
> +       xilinx_pcie_init_port(port);
> +
> +       err = xilinx_pcie_init_irq_domain(port);
> +       if (err) {
> +               dev_err(dev, "Failed creating IRQ Domain\n");
> +               return err;
> +       }
> +
> +       /*
> +        * Parse PCI ranges, configuration bus range and
> +        * request their resources
> +        */
> +       INIT_LIST_HEAD(&port->resources);
> +       err = xilinx_pcie_parse_and_add_res(port);
> +       if (err) {
> +               dev_err(dev, "Failed adding resources\n");
> +               return err;
> +       }
> +
> +       platform_set_drvdata(pdev, port);
> +
> +       /* Register the device */
> +       memset(&hw, 0, sizeof(hw));
> +       hw = (struct hw_pci) {
> +               .nr_controllers = 1,
> +               .private_data   = (void **)&port,
> +               .setup          = xilinx_pcie_setup,
> +               .map_irq        = of_irq_parse_and_map_pci,
> +               .add_bus        = xilinx_pcie_add_bus,
> +               .scan           = xilinx_pcie_scan_bus,
> +               .ops            = &xilinx_pcie_ops,
> +       };
> +       pci_common_init_dev(dev, &hw);
> +
> +       return 0;
> +}
> +
> +/**
> + * xilinx_pcie_remove - Remove function
> + * @pdev: Platform device pointer
> + *
> + * Return: '0' always
> + */
> +static int xilinx_pcie_remove(struct platform_device *pdev)
> +{
> +       struct xilinx_pcie_port *port = platform_get_drvdata(pdev);
> +
> +       xilinx_pcie_free_irq_domain(port);
> +
> +       return 0;
> +}
> +
> +static struct of_device_id xilinx_pcie_of_match[] = {
> +       { .compatible = "xlnx,axi-pcie-host-1.00.a", },
> +       {}
> +};
> +
> +static struct platform_driver xilinx_pcie_driver = {
> +       .driver = {
> +               .name = "xilinx-pcie",
> +               .owner = THIS_MODULE,
> +               .of_match_table = xilinx_pcie_of_match,
> +               .suppress_bind_attrs = true,
> +       },
> +       .probe = xilinx_pcie_probe,
> +       .remove = xilinx_pcie_remove,
> +};
> +module_platform_driver(xilinx_pcie_driver);
> +
> +MODULE_AUTHOR("Xilinx Inc");
> +MODULE_DESCRIPTION("Xilinx AXI PCIe driver");
> +MODULE_LICENSE("GPL v2");
> --
> 1.7.9.5
>
--
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On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
> Hi Arnd and Rob,
> 
> I discussed with Bjorn and we believe this patch is in good shape to
> apply.  And Bjorn requires ACKs to apply this patch.  So, could you
> guys please review this patch and provided your ACKs to this patch.

Looks great for the most part. I've looked through the whole driver
again, and I have two small issues remaining:

a) Please clarify in the changeset description why there is no support
   for PCI I/O space. 

b) I think you should use the 'msi-parent' property, and the
   of_pci_find_msi_chip_by_node() to find the msi_chip for the
   PCI controller. This will make it possible to forward MSIs
   to the main interrupt controller in the system, which is more
   efficient. See the pcie-mvebu driver for an example of this.

Other than these:

Acked-by: Arnd Bergmann <arnd@arndb.de>

	Arnd
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Hi Arnd,

On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>> Hi Arnd and Rob,
>>
>> I discussed with Bjorn and we believe this patch is in good shape to
>> apply.  And Bjorn requires ACKs to apply this patch.  So, could you
>> guys please review this patch and provided your ACKs to this patch.
>
> Looks great for the most part. I've looked through the whole driver
> again, and I have two small issues remaining:
>
> a) Please clarify in the changeset description why there is no support
>    for PCI I/O space.

Sure, I will add to my changeset.

>
> b) I think you should use the 'msi-parent' property, and the
>    of_pci_find_msi_chip_by_node() to find the msi_chip for the
>    PCI controller. This will make it possible to forward MSIs
>    to the main interrupt controller in the system, which is more
>    efficient. See the pcie-mvebu driver for an example of this.

Ok, I need to look into this and I will plan to implement on top of this patch.

>
> Other than these:
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>

Thanks Arnd for the Ack.

Srikanth

>
>         Arnd
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Hi Bjorn,

On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
> Hi Arnd,
> 
> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>>> Hi Arnd and Rob,
>>>
>>> I discussed with Bjorn and we believe this patch is in good shape to
>>> apply.  And Bjorn requires ACKs to apply this patch.  So, could you
>>> guys please review this patch and provided your ACKs to this patch.
>>
>> Looks great for the most part. I've looked through the whole driver
>> again, and I have two small issues remaining:
>>
>> a) Please clarify in the changeset description why there is no support
>>    for PCI I/O space.
> 
> Sure, I will add to my changeset.
> 
>>
>> b) I think you should use the 'msi-parent' property, and the
>>    of_pci_find_msi_chip_by_node() to find the msi_chip for the
>>    PCI controller. This will make it possible to forward MSIs
>>    to the main interrupt controller in the system, which is more
>>    efficient. See the pcie-mvebu driver for an example of this.
> 
> Ok, I need to look into this and I will plan to implement on top of this patch.
> 
>>
>> Other than these:
>>
>> Acked-by: Arnd Bergmann <arnd@arndb.de>
> 
> Thanks Arnd for the Ack.

What's the status on this one?

Srikanth:
Isn't pcie-xilinx.c better name if this is just pcie host bridge?

Thanks,
Michal

Hi Michal,

On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek <monstr@monstr.eu> wrote:
> Hi Bjorn,
>
> On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
>> Hi Arnd,
>>
>> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>>>> Hi Arnd and Rob,
>>>>
>>>> I discussed with Bjorn and we believe this patch is in good shape to
>>>> apply.  And Bjorn requires ACKs to apply this patch.  So, could you
>>>> guys please review this patch and provided your ACKs to this patch.
>>>
>>> Looks great for the most part. I've looked through the whole driver
>>> again, and I have two small issues remaining:
>>>
>>> a) Please clarify in the changeset description why there is no support
>>>    for PCI I/O space.
>>
>> Sure, I will add to my changeset.
>>
>>>
>>> b) I think you should use the 'msi-parent' property, and the
>>>    of_pci_find_msi_chip_by_node() to find the msi_chip for the
>>>    PCI controller. This will make it possible to forward MSIs
>>>    to the main interrupt controller in the system, which is more
>>>    efficient. See the pcie-mvebu driver for an example of this.
>>
>> Ok, I need to look into this and I will plan to implement on top of this patch.
>>
>>>
>>> Other than these:
>>>
>>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>>
>> Thanks Arnd for the Ack.
>
> What's the status on this one?

It looks like Bjorn is on vacation.  I have sent v6 patch by adding
Ack from Arnd, which
I feel is in good shape to be applied.

>
> Srikanth:
> Isn't pcie-xilinx.c better name if this is just pcie host bridge?

Yes, it looks better.  But, many other drivers which are basically
drivers for PCIe host
controllers has the prefix 'pci-' in the file name.  So, I feel it
should be fine and would
be happy to change if I have to.

Thanks
Srikanth

>
> Thanks,
> Michal
>
> --
> Michal Simek, Ing. (M.Eng), OpenPGP -> KeyID: FE3D1F91
> w: www.monstr.eu p: +42-0-721842854
> Maintainer of Linux kernel - Microblaze cpu - http://www.monstr.eu/fdt/
> Maintainer of Linux kernel - Xilinx Zynq ARM architecture
> Microblaze U-BOOT custodian and responsible for u-boot arm zynq platform
>
>
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On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote:
> Hi Michal,
> 
> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek <monstr@monstr.eu> wrote:
> > Hi Bjorn,
> >
> > On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
> >> Hi Arnd,
> >>
> >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann <arnd@arndb.de> wrote:
> >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
> >>>> Hi Arnd and Rob,
> >>>>
> >>>> I discussed with Bjorn and we believe this patch is in good shape to
> >>>> apply.  And Bjorn requires ACKs to apply this patch.  So, could you
> >>>> guys please review this patch and provided your ACKs to this patch.
> >>>
> >>> Looks great for the most part. I've looked through the whole driver
> >>> again, and I have two small issues remaining:
> >>>
> >>> a) Please clarify in the changeset description why there is no support
> >>>    for PCI I/O space.
> >>
> >> Sure, I will add to my changeset.
> >>
> >>>
> >>> b) I think you should use the 'msi-parent' property, and the
> >>>    of_pci_find_msi_chip_by_node() to find the msi_chip for the
> >>>    PCI controller. This will make it possible to forward MSIs
> >>>    to the main interrupt controller in the system, which is more
> >>>    efficient. See the pcie-mvebu driver for an example of this.
> >>
> >> Ok, I need to look into this and I will plan to implement on top of this patch.
> >>
> >>>
> >>> Other than these:
> >>>
> >>> Acked-by: Arnd Bergmann <arnd@arndb.de>
> >>
> >> Thanks Arnd for the Ack.
> >
> > What's the status on this one?
> 
> It looks like Bjorn is on vacation.  I have sent v6 patch by adding
> Ack from Arnd, which
> I feel is in good shape to be applied.

I actually started applying this last night (see [1]), but got some
errors from the build-bot (attached).  I haven't looked into them,
but my guess is that you're missing a Kconfig dependency or something
equally minor.

Bjorn

[1] http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinx&id=a58f3d0c3b1c4a71a2418c3306fba86c26a49781
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git  pci/host-xilinx
a58f3d0c3b1c4a71a2418c3306fba86c26a49781  PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver

drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first use in this function)
drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to incomplete type
drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function 'pci_common_init_dev' [-Werror=implicit-function-declaration]
drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration]
drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type 'struct hw_pci'
drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known
drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified in initializer
drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified in initializer
drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' specified in initializer
drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in initializer
drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' specified in initializer
drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in initializer
drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified in initializer
drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for '(anonymous)')
drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct initializer
drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this definition or declaration, which is probably not what you want
drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of 'sys_to_pcie' from incompatible pointer type
drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared inside parameter list

elapsed time: 25m

configs tested: 112

parisc                        c3000_defconfig
parisc                         b180_defconfig
parisc                              defconfig
alpha                               defconfig
parisc                            allnoconfig
i386                              allnoconfig
i386                                defconfig
i386                             allmodconfig
i386                             alldefconfig
sh                            titan_defconfig
sh                          rsk7269_defconfig
sh                  sh7785lcr_32bit_defconfig
sh                                allnoconfig
x86_64                     randconfig-c3-0818
x86_64                     randconfig-c1-0818
x86_64                     randconfig-c0-0818
x86_64                     randconfig-c2-0818
ia64                             allmodconfig
ia64                              allnoconfig
ia64                                defconfig
ia64                             alldefconfig
x86_64                                    lkp
x86_64                                   rhel
powerpc                      chroma_defconfig
powerpc                 linkstation_defconfig
powerpc                               powerpc
powerpc                         wii_defconfig
powerpc                    gamecube_defconfig
powerpc               corenet64_smp_defconfig
powerpc                               mpc512x
powerpc                                ppc44x
x86_64                     randconfig-j0-0818
x86_64                     randconfig-j1-0818
i386                      randconfig-ha2-0818
i386                      randconfig-ha5-0818
i386                      randconfig-ha4-0818
i386                      randconfig-ha3-0818
i386                      randconfig-ha0-0818
i386                      randconfig-ha1-0818
sparc                               defconfig
sparc64                           allnoconfig
sparc64                             defconfig
x86_64                           allmodconfig
xtensa                       common_defconfig
m32r                       m32104ut_defconfig
xtensa                          iss_defconfig
m32r                         opsput_defconfig
m32r                           usrv_defconfig
m32r                     mappi3.smp_defconfig
i386                          randconfig-i002
i386                          randconfig-i003
i386                          randconfig-i000
i386                          randconfig-i001
i386                          randconfig-i006
i386                          randconfig-i007
i386                          randconfig-i004
i386                          randconfig-i005
i386                          randconfig-i008
i386                          randconfig-i009
x86_64                        randconfig-i009
x86_64                        randconfig-i008
x86_64                        randconfig-i003
x86_64                        randconfig-i002
x86_64                        randconfig-i001
x86_64                        randconfig-i000
x86_64                        randconfig-i007
x86_64                        randconfig-i006
x86_64                        randconfig-i005
x86_64                        randconfig-i004
microblaze                      mmu_defconfig
microblaze                    nommu_defconfig
i386                             allyesconfig
cris                 etrax-100lx_v2_defconfig
blackfin                  TCM-BF537_defconfig
blackfin            BF561-EZKIT-SMP_defconfig
blackfin                BF533-EZKIT_defconfig
blackfin                BF526-EZBRD_defconfig
i386                       randconfig-r2-0818
i386                       randconfig-r1-0818
i386                       randconfig-r0-0818
i386                       randconfig-r3-0818
mn10300                     asb2364_defconfig
openrisc                    or1ksim_defconfig
um                           x86_64_defconfig
um                             i386_defconfig
avr32                      atngw100_defconfig
frv                                 defconfig
avr32                     atstk1006_defconfig
tile                         tilegx_defconfig
x86_64                   randconfig-x004-0817
i386                     randconfig-x000-0817
x86_64                   randconfig-x007-0817
i386                     randconfig-x001-0817
i386                     randconfig-x002-0817
i386                     randconfig-x005-0817
i386                     randconfig-x007-0817
x86_64                   randconfig-x003-0817
i386                     randconfig-x003-0817
x86_64                   randconfig-x008-0817
i386                     randconfig-x006-0817
x86_64                   randconfig-x000-0817
i386                     randconfig-x004-0817
x86_64                   randconfig-x002-0817
i386                     randconfig-x008-0817
i386                     randconfig-x009-0817
x86_64                   randconfig-x006-0817
x86_64                   randconfig-x009-0817
x86_64                   randconfig-x005-0817
x86_64                   randconfig-x001-0817
x86_64                             acpi-redef
x86_64                           allyesdebian
x86_64                                nfsroot

Thanks,
Fengguang
tree:   git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx
head:   a58f3d0c3b1c4a71a2418c3306fba86c26a49781
commit: a58f3d0c3b1c4a71a2418c3306fba86c26a49781 [1/1] PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver
config: make ARCH=arm allmodconfig

All warnings:

>> WARNING: drivers/built-in.o(.text+0x64acc): Section mismatch in reference from the function xilinx_pcie_probe() to the function .init.text:xilinx_pcie_scan_bus()
   The function xilinx_pcie_probe() references
   the function __init xilinx_pcie_scan_bus().
   This is often because xilinx_pcie_probe lacks a __init
   annotation or the annotation of xilinx_pcie_scan_bus is wrong.

---
0-DAY kernel build testing backend              Open Source Technology Center
http://lists.01.org/mailman/listinfo/kbuild                 Intel Corporation

Hi Bjorn,

On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas <bhelgaas@google.com> wrote:
> On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote:
>> Hi Michal,
>>
>> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek <monstr@monstr.eu> wrote:
>> > Hi Bjorn,
>> >
>> > On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
>> >> Hi Arnd,
>> >>
>> >> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann <arnd@arndb.de> wrote:
>> >>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>> >>>> Hi Arnd and Rob,
>> >>>>
>> >>>> I discussed with Bjorn and we believe this patch is in good shape to
>> >>>> apply.  And Bjorn requires ACKs to apply this patch.  So, could you
>> >>>> guys please review this patch and provided your ACKs to this patch.
>> >>>
>> >>> Looks great for the most part. I've looked through the whole driver
>> >>> again, and I have two small issues remaining:
>> >>>
>> >>> a) Please clarify in the changeset description why there is no support
>> >>>    for PCI I/O space.
>> >>
>> >> Sure, I will add to my changeset.
>> >>
>> >>>
>> >>> b) I think you should use the 'msi-parent' property, and the
>> >>>    of_pci_find_msi_chip_by_node() to find the msi_chip for the
>> >>>    PCI controller. This will make it possible to forward MSIs
>> >>>    to the main interrupt controller in the system, which is more
>> >>>    efficient. See the pcie-mvebu driver for an example of this.
>> >>
>> >> Ok, I need to look into this and I will plan to implement on top of this patch.
>> >>
>> >>>
>> >>> Other than these:
>> >>>
>> >>> Acked-by: Arnd Bergmann <arnd@arndb.de>
>> >>
>> >> Thanks Arnd for the Ack.
>> >
>> > What's the status on this one?
>>
>> It looks like Bjorn is on vacation.  I have sent v6 patch by adding
>> Ack from Arnd, which
>> I feel is in good shape to be applied.
>
> I actually started applying this last night (see [1]), but got some
> errors from the build-bot (attached).  I haven't looked into them,
> but my guess is that you're missing a Kconfig dependency or something
> equally minor.

These are due to the same config flag name (CONFIG_PCI_XILINX) being used
for Microblaze and Zynq platforms.  I will fix it and send you next
version of patch.

Thanks,
Srikanth

>
> Bjorn
>
> [1] http://git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git/commit/?h=pci/host-xilinx&id=a58f3d0c3b1c4a71a2418c3306fba86c26a49781
>
>
> ---------- Forwarded message ----------
> From: kbuild test robot <fengguang.wu@intel.com>
> To: Bjorn Helgaas <bhelgaas@google.com>
> Cc:
> Date: Mon, 18 Aug 2014 12:40:06 +0800
> Subject: [pci:pci/host-xilinx] a58f3d0c3b1c4a71a2418c3306fba86c26a49781 BUILD DONE
> git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git  pci/host-xilinx
> a58f3d0c3b1c4a71a2418c3306fba86c26a49781  PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver
>
> drivers/pci/host/pci-xilinx.c:470:21: error: 'IRQF_VALID' undeclared (first use in this function)
> drivers/pci/host/pci-xilinx.c:742:14: error: dereferencing pointer to incomplete type
> drivers/pci/host/pci-xilinx.c:939:2: error: implicit declaration of function 'pci_common_init_dev' [-Werror=implicit-function-declaration]
> drivers/pci/host/pci-xilinx.c:417:2: error: implicit declaration of function 'set_irq_flags' [-Werror=implicit-function-declaration]
> drivers/pci/host/pci-xilinx.c:938:2: error: invalid use of undefined type 'struct hw_pci'
> drivers/pci/host/pci-xilinx.c:888:16: error: storage size of 'hw' isn't known
> drivers/pci/host/pci-xilinx.c:935:3: error: unknown field 'add_bus' specified in initializer
> drivers/pci/host/pci-xilinx.c:934:3: error: unknown field 'map_irq' specified in initializer
> drivers/pci/host/pci-xilinx.c:931:3: error: unknown field 'nr_controllers' specified in initializer
> drivers/pci/host/pci-xilinx.c:937:3: error: unknown field 'ops' specified in initializer
> drivers/pci/host/pci-xilinx.c:932:3: error: unknown field 'private_data' specified in initializer
> drivers/pci/host/pci-xilinx.c:936:3: error: unknown field 'scan' specified in initializer
> drivers/pci/host/pci-xilinx.c:933:3: error: unknown field 'setup' specified in initializer
> drivers/pci/host/pci-xilinx.c:937:3: warning: (near initialization for '(anonymous)')
> drivers/pci/host/pci-xilinx.c:937:3: warning: excess elements in struct initializer
> drivers/pci/host/pci-xilinx.c:124:59: warning: its scope is only this definition or declaration, which is probably not what you want
> drivers/pci/host/pci-xilinx.c:737:34: warning: passing argument 1 of 'sys_to_pcie' from incompatible pointer type
> drivers/pci/host/pci-xilinx.c:735:17: warning: 'struct pci_sys_data' declared inside parameter list
>
> elapsed time: 25m
>
> configs tested: 112
>
> parisc                        c3000_defconfig
> parisc                         b180_defconfig
> parisc                              defconfig
> alpha                               defconfig
> parisc                            allnoconfig
> i386                              allnoconfig
> i386                                defconfig
> i386                             allmodconfig
> i386                             alldefconfig
> sh                            titan_defconfig
> sh                          rsk7269_defconfig
> sh                  sh7785lcr_32bit_defconfig
> sh                                allnoconfig
> x86_64                     randconfig-c3-0818
> x86_64                     randconfig-c1-0818
> x86_64                     randconfig-c0-0818
> x86_64                     randconfig-c2-0818
> ia64                             allmodconfig
> ia64                              allnoconfig
> ia64                                defconfig
> ia64                             alldefconfig
> x86_64                                    lkp
> x86_64                                   rhel
> powerpc                      chroma_defconfig
> powerpc                 linkstation_defconfig
> powerpc                               powerpc
> powerpc                         wii_defconfig
> powerpc                    gamecube_defconfig
> powerpc               corenet64_smp_defconfig
> powerpc                               mpc512x
> powerpc                                ppc44x
> x86_64                     randconfig-j0-0818
> x86_64                     randconfig-j1-0818
> i386                      randconfig-ha2-0818
> i386                      randconfig-ha5-0818
> i386                      randconfig-ha4-0818
> i386                      randconfig-ha3-0818
> i386                      randconfig-ha0-0818
> i386                      randconfig-ha1-0818
> sparc                               defconfig
> sparc64                           allnoconfig
> sparc64                             defconfig
> x86_64                           allmodconfig
> xtensa                       common_defconfig
> m32r                       m32104ut_defconfig
> xtensa                          iss_defconfig
> m32r                         opsput_defconfig
> m32r                           usrv_defconfig
> m32r                     mappi3.smp_defconfig
> i386                          randconfig-i002
> i386                          randconfig-i003
> i386                          randconfig-i000
> i386                          randconfig-i001
> i386                          randconfig-i006
> i386                          randconfig-i007
> i386                          randconfig-i004
> i386                          randconfig-i005
> i386                          randconfig-i008
> i386                          randconfig-i009
> x86_64                        randconfig-i009
> x86_64                        randconfig-i008
> x86_64                        randconfig-i003
> x86_64                        randconfig-i002
> x86_64                        randconfig-i001
> x86_64                        randconfig-i000
> x86_64                        randconfig-i007
> x86_64                        randconfig-i006
> x86_64                        randconfig-i005
> x86_64                        randconfig-i004
> microblaze                      mmu_defconfig
> microblaze                    nommu_defconfig
> i386                             allyesconfig
> cris                 etrax-100lx_v2_defconfig
> blackfin                  TCM-BF537_defconfig
> blackfin            BF561-EZKIT-SMP_defconfig
> blackfin                BF533-EZKIT_defconfig
> blackfin                BF526-EZBRD_defconfig
> i386                       randconfig-r2-0818
> i386                       randconfig-r1-0818
> i386                       randconfig-r0-0818
> i386                       randconfig-r3-0818
> mn10300                     asb2364_defconfig
> openrisc                    or1ksim_defconfig
> um                           x86_64_defconfig
> um                             i386_defconfig
> avr32                      atngw100_defconfig
> frv                                 defconfig
> avr32                     atstk1006_defconfig
> tile                         tilegx_defconfig
> x86_64                   randconfig-x004-0817
> i386                     randconfig-x000-0817
> x86_64                   randconfig-x007-0817
> i386                     randconfig-x001-0817
> i386                     randconfig-x002-0817
> i386                     randconfig-x005-0817
> i386                     randconfig-x007-0817
> x86_64                   randconfig-x003-0817
> i386                     randconfig-x003-0817
> x86_64                   randconfig-x008-0817
> i386                     randconfig-x006-0817
> x86_64                   randconfig-x000-0817
> i386                     randconfig-x004-0817
> x86_64                   randconfig-x002-0817
> i386                     randconfig-x008-0817
> i386                     randconfig-x009-0817
> x86_64                   randconfig-x006-0817
> x86_64                   randconfig-x009-0817
> x86_64                   randconfig-x005-0817
> x86_64                   randconfig-x001-0817
> x86_64                             acpi-redef
> x86_64                           allyesdebian
> x86_64                                nfsroot
>
> Thanks,
> Fengguang
>
>
> ---------- Forwarded message ----------
> From: kbuild test robot <fengguang.wu@intel.com>
> To: Srikanth Thokala <sthokal@xilinx.com>
> Cc: Bjorn Helgaas <bhelgaas@google.com>, kbuild-all@01.org
> Date: Mon, 18 Aug 2014 15:16:51 +0800
> Subject: [pci:pci/host-xilinx 1/1] WARNING: drivers/built-in.o(.text+0x64acc): Section mismatch in reference from the function xilinx_pcie_probe() to the function .init.text:xilinx_pcie_scan_bus()
> tree:   git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-xilinx
> head:   a58f3d0c3b1c4a71a2418c3306fba86c26a49781
> commit: a58f3d0c3b1c4a71a2418c3306fba86c26a49781 [1/1] PCI: xilinx: Add Xilinx PCIe Host Bridge IP driver
> config: make ARCH=arm allmodconfig
>
> All warnings:
>
>>> WARNING: drivers/built-in.o(.text+0x64acc): Section mismatch in reference from the function xilinx_pcie_probe() to the function .init.text:xilinx_pcie_scan_bus()
>    The function xilinx_pcie_probe() references
>    the function __init xilinx_pcie_scan_bus().
>    This is often because xilinx_pcie_probe lacks a __init
>    annotation or the annotation of xilinx_pcie_scan_bus is wrong.
>
> ---
> 0-DAY kernel build testing backend              Open Source Technology Center
> http://lists.01.org/mailman/listinfo/kbuild                 Intel Corporation
>
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