diff mbox

[AArch64/GCC,7/N] Hoist calculation of register rtx

Message ID 53CE7A6C.7000503@arm.com
State New
Headers show

Commit Message

Jiong Wang July 22, 2014, 2:51 p.m. UTC
This patch hoist the calcuation of register rtx to avoid invoking
of "gen_rtx_REG" scattered everywhere.

*no functional change*

ok to install?

thanks.

gcc/
   * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Hoist calculation
   of register rtx.
   (aarch64_save_or_restore_callee_save_registers): Likewise.

Comments

Marcus Shawcroft July 23, 2014, 4:13 p.m. UTC | #1
On 22 July 2014 15:51, Jiong Wang <jiong.wang@arm.com> wrote:

> gcc/
>   * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Hoist
> calculation
>   of register rtx.
>   (aarch64_save_or_restore_callee_save_registers): Likewise.

OK and applied.
/Marcus
diff mbox

Patch

>From 0c56d2136d65b44311cd9af2e4e2b173e823a17a Mon Sep 17 00:00:00 2001
From: Jiong Wang <jiong.wang@arm.com>
Date: Tue, 17 Jun 2014 21:43:05 +0100
Subject: [PATCH 07/19] [AArch64/GCC][7/20]Hoist calculation of register rtx

This patch hoist the calcuation of register rtx to avoid invoking
of "gen_rtx_REG" scattered everywhere.

*no functional change*

2014-06-16  Jiong Wang <jiong.wang@arm.com>
	    Marcus Shawcroft  <marcus.shawcroft@arm.com>

gcc/
  * config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Hoist calculation
  of register rtx.
  (aarch64_save_or_restore_callee_save_registers): Likewise.
---
 gcc/config/aarch64/aarch64.c |   54 ++++++++++++++----------------------------
 1 file changed, 18 insertions(+), 36 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 1c2d2fb..07358fe 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -1919,6 +1919,7 @@  aarch64_save_or_restore_fprs (HOST_WIDE_INT start_offset, bool restore)
     {
       if (aarch64_register_saved_on_entry (regno))
 	{
+	  rtx reg = gen_rtx_REG (DFmode, regno);
 	  rtx mem;
 
 	  HOST_WIDE_INT offset = start_offset
@@ -1937,6 +1938,7 @@  aarch64_save_or_restore_fprs (HOST_WIDE_INT start_offset, bool restore)
 	  if (regno2 <= V31_REGNUM
 	      && aarch64_register_saved_on_entry (regno2))
 	    {
+	      rtx reg2 = gen_rtx_REG (DFmode, regno2);
 	      rtx mem2;
 
 	      offset = start_offset + cfun->machine->frame.reg_offset[regno2];
@@ -1944,22 +1946,12 @@  aarch64_save_or_restore_fprs (HOST_WIDE_INT start_offset, bool restore)
 				  plus_constant (Pmode, stack_pointer_rtx,
 						 offset));
 	      if (restore == false)
-		{
-		  insn = emit_insn
-		    (gen_store_pairdf (mem, gen_rtx_REG (DFmode, regno),
-				       mem2, gen_rtx_REG (DFmode, regno2)));
-
-		}
+		insn = emit_insn (gen_store_pairdf (mem, reg, mem2, reg2));
 	      else
 		{
-		  insn = emit_insn
-		    (gen_load_pairdf (gen_rtx_REG (DFmode, regno), mem,
-				      gen_rtx_REG (DFmode, regno2), mem2));
-
-		  add_reg_note (insn, REG_CFA_RESTORE,
-				gen_rtx_REG (DFmode, regno));
-		  add_reg_note (insn, REG_CFA_RESTORE,
-				gen_rtx_REG (DFmode, regno2));
+		  insn = emit_insn (gen_load_pairdf (reg, mem, reg2, mem2));
+		  add_reg_note (insn, REG_CFA_RESTORE, reg);
+		  add_reg_note (insn, REG_CFA_RESTORE, reg2);
 		}
 
 	      /* The first part of a frame-related parallel insn is
@@ -1972,12 +1964,11 @@  aarch64_save_or_restore_fprs (HOST_WIDE_INT start_offset, bool restore)
 	  else
 	    {
 	      if (restore == false)
-		insn = emit_move_insn (mem, gen_rtx_REG (DFmode, regno));
+		insn = emit_move_insn (mem, reg);
 	      else
 		{
-		  insn = emit_move_insn (gen_rtx_REG (DFmode, regno), mem);
-		  add_reg_note (insn, REG_CFA_RESTORE,
-				gen_rtx_REG (DFmode, regno));
+		  insn = emit_move_insn (reg, mem);
+		  add_reg_note (insn, REG_CFA_RESTORE, reg);
 		}
 	    }
 	  RTX_FRAME_RELATED_P (insn) = 1;
@@ -2003,6 +1994,7 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
     {
       if (aarch64_register_saved_on_entry (regno))
 	{
+	  rtx reg = gen_rtx_REG (DImode, regno);
 	  rtx mem;
 
 	  HOST_WIDE_INT offset = start_offset
@@ -2023,6 +2015,7 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
 	      && ((cfun->machine->frame.reg_offset[regno] + UNITS_PER_WORD)
 		  == cfun->machine->frame.reg_offset[regno2]))
 	    {
+	      rtx reg2 = gen_rtx_REG (DImode, regno2);
 	      rtx mem2;
 
 	      offset = start_offset + cfun->machine->frame.reg_offset[regno2];
@@ -2030,22 +2023,12 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
 				  plus_constant (Pmode, stack_pointer_rtx,
 						 offset));
 	      if (restore == false)
-		{
-		  insn = emit_insn
-		    (gen_store_pairdi (mem, gen_rtx_REG (DImode, regno),
-				       mem2, gen_rtx_REG (DImode, regno2)));
-
-		}
+		  insn = emit_insn (gen_store_pairdi (mem, reg, mem2, reg2));
 	      else
 		{
-		  insn = emit_insn
-		    (gen_load_pairdi (gen_rtx_REG (DImode, regno), mem,
-				      gen_rtx_REG (DImode, regno2), mem2));
-
-		  add_reg_note (insn, REG_CFA_RESTORE,
-				gen_rtx_REG (DImode, regno));
-		  add_reg_note (insn, REG_CFA_RESTORE,
-				gen_rtx_REG (DImode, regno2));
+		  insn = emit_insn (gen_load_pairdi (reg, mem, reg2, mem2));
+		  add_reg_note (insn, REG_CFA_RESTORE, reg);
+		  add_reg_note (insn, REG_CFA_RESTORE, reg2);
 		}
 
 	      /* The first part of a frame-related parallel insn is
@@ -2058,12 +2041,11 @@  aarch64_save_or_restore_callee_save_registers (HOST_WIDE_INT start_offset,
 	  else
 	    {
 	      if (restore == false)
-		insn = emit_move_insn (mem, gen_rtx_REG (DImode, regno));
+		insn = emit_move_insn (mem, reg);
 	      else
 		{
-		  insn = emit_move_insn (gen_rtx_REG (DImode, regno), mem);
-		  add_reg_note (insn, REG_CFA_RESTORE,
-				gen_rtx_REG (DImode, regno));
+		  insn = emit_move_insn (reg, mem);
+		  add_reg_note (insn, REG_CFA_RESTORE, reg);
 		}
 	    }
 	  RTX_FRAME_RELATED_P (insn) = 1;
-- 
1.7.9.5