diff mbox

ARM: tegra: paz00: Fix some indentation inconsistencies

Message ID 1405943948-3209-1-git-send-email-thierry.reding@gmail.com
State Accepted, archived
Headers show

Commit Message

Thierry Reding July 21, 2014, 11:59 a.m. UTC 
From: Thierry Reding <treding@nvidia.com>

Indentation of the clock property used a hodgepodge of tabs and spaces.
Make them more consistent (tabs for indentation followed by spaces for
alignment).

Signed-off-by: Thierry Reding <treding@nvidia.com>
---
 arch/arm/boot/dts/tegra20-paz00.dts | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

Comments

Stephen Warren July 21, 2014, 3:07 p.m. UTC | #1 
On 07/21/2014 05:59 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
> 
> Indentation of the clock property used a hodgepodge of tabs and spaces.
> Make them more consistent (tabs for indentation followed by spaces for
> alignment).

Acked-by: Stephen Warren <swarren@nvidia.com>
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Stephen Warren July 25, 2014, 6:41 p.m. UTC | #2 
On 07/21/2014 05:59 AM, Thierry Reding wrote:
> From: Thierry Reding <treding@nvidia.com>
>
> Indentation of the clock property used a hodgepodge of tabs and spaces.
> Make them more consistent (tabs for indentation followed by spaces for
> alignment).

I've forwarded this patch to the arm-soc maintainers to apply directly.
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diff mbox

Patch

diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 9a39a8001f78..d4438e30de45 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -296,7 +296,7 @@ 
 		request-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>;
 		slave-addr = <138>;
 		clocks = <&tegra_car TEGRA20_CLK_I2C3>,
-		       	 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
+		         <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
 		clock-names = "div-clk", "fast-clk";
 		resets = <&tegra_car 67>;
 		reset-names = "i2c";
@@ -589,8 +589,8 @@ 
 			GPIO_ACTIVE_HIGH>;
 
 		clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
-		       	 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
-			 <&tegra_car TEGRA20_CLK_CDEV1>;
+		         <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
+		         <&tegra_car TEGRA20_CLK_CDEV1>;
 		clock-names = "pll_a", "pll_a_out0", "mclk";
 	};
 };