Patchwork [committed] Fix umips-lwp-*.c tests

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Submitter Richard Sandiford
Date July 17, 2014, 7:36 p.m.
Message ID <87oawnpyjx.fsf@talisman.default>
Download mbox | patch
Permalink /patch/371249/
State New
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Comments

Richard Sandiford - July 17, 2014, 7:36 p.m.
umips-lwp-[1234].c test that two loads from consecutive memory locations
to consecutive registers ($5 and $6) can use LWP.  The idea was to have
2 tests where $5 was loaded first before $6 and 2 tests that were the
other way around (at least when scheduling is enabled).  I'd tried to force
that by having one register involved in multiplication and so obviously
on the critical path.  However, the multiplication and store now happen
before the load of the other register, which defeats the point of the
thing and makes the test fail.

Here I've used a shift and add sequence instead, after verifying that
the pre-peephole2 orderings are still different for 1,3 vs. 2,4.

Tested on mips64-linux-gnu and applied.

Thanks,
Richard


gcc/testsuite/
	* gcc.target/mips/umips-lwp-1.c (foo): Use a shift/add sequence
	involving both inputs rather than a multiplication involving one.
	* gcc.target/mips/umips-lwp-2.c (foo): Likewise.
	* gcc.target/mips/umips-lwp-3.c (foo): Likewise.
	* gcc.target/mips/umips-lwp-4.c (foo): Likewise.

Patch

Index: gcc/testsuite/gcc.target/mips/umips-lwp-1.c
===================================================================
--- gcc/testsuite/gcc.target/mips/umips-lwp-1.c	2014-07-17 20:17:43.255936742 +0100
+++ gcc/testsuite/gcc.target/mips/umips-lwp-1.c	2014-07-17 20:27:46.543603109 +0100
@@ -6,7 +6,7 @@  foo (int *r4)
 {
   int r5 = r4[0];
   int r6 = r4[1];
-  r4[2] = r5 * r5;
+  r4[2] = (r5 << 1) + r6;
   {
     register int r5asm asm ("$5") = r5;
     register int r6asm asm ("$6") = r6;
Index: gcc/testsuite/gcc.target/mips/umips-lwp-2.c
===================================================================
--- gcc/testsuite/gcc.target/mips/umips-lwp-2.c	2014-04-25 10:40:00.806595073 +0100
+++ gcc/testsuite/gcc.target/mips/umips-lwp-2.c	2014-07-17 20:28:03.451761888 +0100
@@ -6,7 +6,7 @@  foo (int *r4)
 {
   int r5 = r4[0];
   int r6 = r4[1];
-  r4[2] = r6 * r6;
+  r4[2] = (r6 << 1) + r5;
   {
     register int r5asm asm ("$5") = r5;
     register int r6asm asm ("$6") = r6;
Index: gcc/testsuite/gcc.target/mips/umips-lwp-3.c
===================================================================
--- gcc/testsuite/gcc.target/mips/umips-lwp-3.c	2014-04-25 10:40:00.995596575 +0100
+++ gcc/testsuite/gcc.target/mips/umips-lwp-3.c	2014-07-17 20:28:38.133087563 +0100
@@ -6,7 +6,7 @@  foo (int *r4)
 {
   int r5 = r4[511];
   int r6 = r4[512];
-  r4[2] = r5 * r5;
+  r4[2] = (r5 << 1) + r6;
   {
     register int r5asm asm ("$5") = r5;
     register int r6asm asm ("$6") = r6;
Index: gcc/testsuite/gcc.target/mips/umips-lwp-4.c
===================================================================
--- gcc/testsuite/gcc.target/mips/umips-lwp-4.c	2014-04-25 10:40:01.222598380 +0100
+++ gcc/testsuite/gcc.target/mips/umips-lwp-4.c	2014-07-17 20:28:46.754168518 +0100
@@ -6,7 +6,7 @@  foo (int *r4)
 {
   int r5 = r4[511];
   int r6 = r4[512];
-  r4[2] = r6 * r6;
+  r4[2] = (r6 << 1) + r5;
   {
     register int r5asm asm ("$5") = r5;
     register int r6asm asm ("$6") = r6;