| Message ID | 1405521777-24085-3-git-send-email-aggelerf@ethz.ch |
|---|---|
| State | New |
| Headers | show |
Fabian Aggeler writes: > The SP810, which is present in the Versatile Express motherboards, > allows to set the timing reference to either REFCLK or TIMCLK. > QEMU currently sets the SP804 timer to 1MHz by default. To reflect > this, we set the TimerEn0Sel, TimerEn1Sel, TimerEn2Sel, and > TimerEn3Sel of the system control register (SCCTRL) to TIMCLK (1). > > Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> > --- > hw/arm/vexpress.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c > index a88732c..b96c3fd 100644 > --- a/hw/arm/vexpress.c > +++ b/hw/arm/vexpress.c > @@ -512,7 +512,7 @@ static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, > static void vexpress_common_init(VEDBoardInfo *daughterboard, > MachineState *machine) > { > - DeviceState *dev, *sysctl, *pl041; > + DeviceState *dev, *sysctl, *pl041, *sp810; > qemu_irq pic[64]; > uint32_t sys_id; > DriveInfo *dinfo; > @@ -575,7 +575,14 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, > qdev_init_nofail(sysctl); > sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); > > - /* VE_SP810: not modelled */ > + /* VE_SP810 */ > + sp810 = qdev_create(NULL, "arm_sp810"); > + /* SP804 is already running at 1MHz (TIMCLK) so SCCTRL TimerEnXSel=1 */ > + qdev_prop_set_uint32(sp810, "sc-ctrl", (1 << 15) | (1 << 17) > + | (1 << 19) | (1 << 21)); <snip> Could the #defines in the first patch be moved into a header and used here rather than manually setting these bits?
On Thu, Jul 17, 2014 at 1:05 AM, Alex Bennée <alex.bennee@linaro.org> wrote: > > Fabian Aggeler writes: > >> The SP810, which is present in the Versatile Express motherboards, >> allows to set the timing reference to either REFCLK or TIMCLK. >> QEMU currently sets the SP804 timer to 1MHz by default. To reflect >> this, we set the TimerEn0Sel, TimerEn1Sel, TimerEn2Sel, and >> TimerEn3Sel of the system control register (SCCTRL) to TIMCLK (1). >> >> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> >> --- >> hw/arm/vexpress.c | 11 +++++++++-- >> 1 file changed, 9 insertions(+), 2 deletions(-) >> >> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c >> index a88732c..b96c3fd 100644 >> --- a/hw/arm/vexpress.c >> +++ b/hw/arm/vexpress.c >> @@ -512,7 +512,7 @@ static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, >> static void vexpress_common_init(VEDBoardInfo *daughterboard, >> MachineState *machine) >> { >> - DeviceState *dev, *sysctl, *pl041; >> + DeviceState *dev, *sysctl, *pl041, *sp810; >> qemu_irq pic[64]; >> uint32_t sys_id; >> DriveInfo *dinfo; >> @@ -575,7 +575,14 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, >> qdev_init_nofail(sysctl); >> sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); >> >> - /* VE_SP810: not modelled */ >> + /* VE_SP810 */ >> + sp810 = qdev_create(NULL, "arm_sp810"); Move the the type definition macro to header as well. Regards, Peter >> + /* SP804 is already running at 1MHz (TIMCLK) so SCCTRL TimerEnXSel=1 */ >> + qdev_prop_set_uint32(sp810, "sc-ctrl", (1 << 15) | (1 << 17) >> + | (1 << 19) | (1 << 21)); > <snip> > > Could the #defines in the first patch be moved into a header and used > here rather than manually setting these bits? > > -- > Alex Bennée >
On 17 Jul 2014, at 01:29, Peter Crosthwaite <peter.crosthwaite@xilinx.com> wrote: > On Thu, Jul 17, 2014 at 1:05 AM, Alex Bennée <alex.bennee@linaro.org> wrote: >> >> Fabian Aggeler writes: >> >>> The SP810, which is present in the Versatile Express motherboards, >>> allows to set the timing reference to either REFCLK or TIMCLK. >>> QEMU currently sets the SP804 timer to 1MHz by default. To reflect >>> this, we set the TimerEn0Sel, TimerEn1Sel, TimerEn2Sel, and >>> TimerEn3Sel of the system control register (SCCTRL) to TIMCLK (1). >>> >>> Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> >>> --- >>> hw/arm/vexpress.c | 11 +++++++++-- >>> 1 file changed, 9 insertions(+), 2 deletions(-) >>> >>> diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c >>> index a88732c..b96c3fd 100644 >>> --- a/hw/arm/vexpress.c >>> +++ b/hw/arm/vexpress.c >>> @@ -512,7 +512,7 @@ static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, >>> static void vexpress_common_init(VEDBoardInfo *daughterboard, >>> MachineState *machine) >>> { >>> - DeviceState *dev, *sysctl, *pl041; >>> + DeviceState *dev, *sysctl, *pl041, *sp810; >>> qemu_irq pic[64]; >>> uint32_t sys_id; >>> DriveInfo *dinfo; >>> @@ -575,7 +575,14 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, >>> qdev_init_nofail(sysctl); >>> sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); >>> >>> - /* VE_SP810: not modelled */ >>> + /* VE_SP810 */ >>> + sp810 = qdev_create(NULL, "arm_sp810"); > > Move the the type definition macro to header as well. > > Regards, > Peter Thanks for your comments. I addressed them in v2 which I am going to send shortly. Best, Fabian > >>> + /* SP804 is already running at 1MHz (TIMCLK) so SCCTRL TimerEnXSel=1 */ >>> + qdev_prop_set_uint32(sp810, "sc-ctrl", (1 << 15) | (1 << 17) >>> + | (1 << 19) | (1 << 21)); >> <snip> >> >> Could the #defines in the first patch be moved into a header and used >> here rather than manually setting these bits? >> >> -- >> Alex Bennée
diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index a88732c..b96c3fd 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -512,7 +512,7 @@ static pflash_t *ve_pflash_cfi01_register(hwaddr base, const char *name, static void vexpress_common_init(VEDBoardInfo *daughterboard, MachineState *machine) { - DeviceState *dev, *sysctl, *pl041; + DeviceState *dev, *sysctl, *pl041, *sp810; qemu_irq pic[64]; uint32_t sys_id; DriveInfo *dinfo; @@ -575,7 +575,14 @@ static void vexpress_common_init(VEDBoardInfo *daughterboard, qdev_init_nofail(sysctl); sysbus_mmio_map(SYS_BUS_DEVICE(sysctl), 0, map[VE_SYSREGS]); - /* VE_SP810: not modelled */ + /* VE_SP810 */ + sp810 = qdev_create(NULL, "arm_sp810"); + /* SP804 is already running at 1MHz (TIMCLK) so SCCTRL TimerEnXSel=1 */ + qdev_prop_set_uint32(sp810, "sc-ctrl", (1 << 15) | (1 << 17) + | (1 << 19) | (1 << 21)); + qdev_init_nofail(sp810); + sysbus_mmio_map(SYS_BUS_DEVICE(sp810), 0, map[VE_SP810]); + /* VE_SERIALPCI: not modelled */ pl041 = qdev_create(NULL, "pl041");
The SP810, which is present in the Versatile Express motherboards, allows to set the timing reference to either REFCLK or TIMCLK. QEMU currently sets the SP804 timer to 1MHz by default. To reflect this, we set the TimerEn0Sel, TimerEn1Sel, TimerEn2Sel, and TimerEn3Sel of the system control register (SCCTRL) to TIMCLK (1). Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> --- hw/arm/vexpress.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)