diff mbox

[v2,15/15] target-tricore: Add instructions of SR opcode format

Message ID 1405359671-25985-16-git-send-email-kbastian@mail.uni-paderborn.de
State New
Headers show

Commit Message

Bastian Koppelmann July 14, 2014, 5:41 p.m. UTC 
Add instructions of SR opcode format.
Add micro-op generator functions for saturate.
Add helper return from exception (rfe).

Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
---
v1 -> v2:
    - Change cdc_zero using clo32 instead of a loop.
    - Change gen_saturate/_h using movecond instead of a branch.
    - Remove rsubi and use subfi_tl instead.
    - Change SR_JI instruction to use the right mask.
    - Remove BS_STOP on NOP isntruction.
    - Add BS_BRANCH and tcg_gen_exit_tb on RFE instruction.
    - Remove BS_STOP of DEBUG instructions.
    - Remove printfs.

 target-tricore/helper.h    |   1 +
 target-tricore/op_helper.c |  51 +++++++++++++++++++++++
 target-tricore/translate.c | 101 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 153 insertions(+)

--
2.0.1

Comments

Richard Henderson July 15, 2014, 4:50 p.m. UTC | #1 
On 07/14/2014 10:41 AM, Bastian Koppelmann wrote:
> +static bool cdc_zero(target_ulong *psw)
> +{
> +    int cdc = *psw & MASK_PSW_CDC;
> +    /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
> +       7'b1111111, otherwise returns FALSE. */
> +    if (cdc == 0x7f) {
> +        return true;
> +    }
> +    /* find CDC.COUNT */
> +    if (((1 << (6 - clo32(*psw & MASK_PSW_CDC))) - 1) == 0) {
> +        return true;
> +    }
> +
> +    return false;
> +}

You've misunderstood me wrt clo.  As written here, it'll always return 0, since
the value you're passing is zero-extended to 32 bits.

Something like

  int lo = clo32((*psw & MASK_PSW_CDC) << (32 - 7));
  int mask = (1u << (7 - lo)) - 1;
  int count = *psw & mask;
  return count == 0;

> +static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
> +{
> +    TCGv sat_neg = tcg_const_i32(low);
> +    TCGv temp = tcg_const_i32(up);
> +
> +    /* sat_neg = (arg < low ) ? low : arg; */
> +    tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, arg, sat_neg);
> +
> +    /* ret = (sat_neg > up ) ? up  : sat_neg; */
> +    tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
> +
> +    tcg_temp_free(sat_neg);

Forgot to free temp.

> +    case OPC2_16_SR_RSUB:
> +        tcg_gen_subfi_tl(cpu_gpr_d[r1], 0, cpu_gpr_d[r1]);
> +        break;

tcg_gen_neg_tl.


r~
diff mbox

Patch

diff --git a/target-tricore/helper.h b/target-tricore/helper.h
index ce64dc2..b0c7ba7 100644
--- a/target-tricore/helper.h
+++ b/target-tricore/helper.h
@@ -23,3 +23,4 @@  DEF_HELPER_3(sub_ssov, i32, env, i32, i32)
 DEF_HELPER_2(call, void, env, i32)
 DEF_HELPER_1(ret, void, env)
 DEF_HELPER_2(bisr, void, env, i32)
+DEF_HELPER_1(rfe, void, env)
diff --git a/target-tricore/op_helper.c b/target-tricore/op_helper.c
index 862b255..92105e4 100644
--- a/target-tricore/op_helper.c
+++ b/target-tricore/op_helper.c
@@ -125,6 +125,22 @@  static int cdc_decrement(target_ulong *psw)
     return 0;
 }

+static bool cdc_zero(target_ulong *psw)
+{
+    int cdc = *psw & MASK_PSW_CDC;
+    /* Returns TRUE if PSW.CDC.COUNT == 0 or if PSW.CDC ==
+       7'b1111111, otherwise returns FALSE. */
+    if (cdc == 0x7f) {
+        return true;
+    }
+    /* find CDC.COUNT */
+    if (((1 << (6 - clo32(*psw & MASK_PSW_CDC))) - 1) == 0) {
+        return true;
+    }
+
+    return false;
+}
+
 static void save_context_upper(CPUTRICOREState *env, int ea,
                                target_ulong *new_FCX)
 {
@@ -315,6 +331,41 @@  void helper_bisr(CPUTRICOREState *env, uint32_t const9)
     }
 }

+void helper_rfe(CPUTRICOREState *env)
+{
+    target_ulong ea;
+    target_ulong new_PCXI;
+    target_ulong new_PSW;
+    /* if (PCXI[19: 0] == 0) then trap(CSU); */
+    if ((env->PCXI & 0xfffff) == 0) {
+        /* raise csu trap */
+    }
+    /* if (PCXI.UL == 0) then trap(CTYP); */
+    if ((env->PCXI & MASK_PCXI_UL) == 0) {
+        /* raise CTYP trap */
+    }
+    /* if (!cdc_zero() AND PSW.CDE) then trap(NEST); */
+    if (!cdc_zero(&(env->PSW)) && (env->PSW & MASK_PSW_CDE)) {
+        /* raise MNG trap */
+    }
+    /* ICR.IE = PCXI.PIE; */
+    env->ICR = (env->ICR & ~MASK_ICR_IE) + ((env->PCXI & MASK_PCXI_PIE) >> 15);
+    /* ICR.CCPN = PCXI.PCPN; */
+    env->ICR = (env->ICR & ~MASK_ICR_CCPN) +
+               ((env->PCXI & MASK_PCXI_PCPN) >> 24);
+    /*EA = {PCXI.PCXS, 6'b0, PCXI.PCXO, 6'b0};*/
+    ea = ((env->PCXI & MASK_PCXI_PCXS) << 12) +
+         ((env->PCXI & MASK_PCXI_PCXO) << 6);
+    /*{new_PCXI, PSW, A[10], A[11], D[8], D[9], D[10], D[11], A[12],
+      A[13], A[14], A[15], D[12], D[13], D[14], D[15]} = M(EA, 16 * word);
+      M(EA, word) = FCX;*/
+    restore_context_upper(env, ea, &new_PCXI, &new_PSW);
+    /* FCX[19: 0] = PCXI[19: 0]; */
+    env->FCX = (env->FCX & 0xfff00000) + (env->PCXI & 0x000fffff);
+    /* PCXI = new_PCXI; */
+    env->PCXI = new_PCXI;
+}
+
 static inline void QEMU_NORETURN do_raise_exception_err(CPUTRICOREState *env,
                                                         uint32_t exception,
                                                         int error_code,
diff --git a/target-tricore/translate.c b/target-tricore/translate.c
index dc2a6bc..6f5d932 100644
--- a/target-tricore/translate.c
+++ b/target-tricore/translate.c
@@ -128,6 +128,30 @@  static inline void gen_offset_st(DisasContext *ctx, TCGv r1, TCGv r2,

 /* Functions for arithmetic instructions  */

+static void gen_saturate(TCGv ret, TCGv arg, int32_t up, int32_t low)
+{
+    TCGv sat_neg = tcg_const_i32(low);
+    TCGv temp = tcg_const_i32(up);
+
+    /* sat_neg = (arg < low ) ? low : arg; */
+    tcg_gen_movcond_tl(TCG_COND_LT, sat_neg, arg, sat_neg, arg, sat_neg);
+
+    /* ret = (sat_neg > up ) ? up  : sat_neg; */
+    tcg_gen_movcond_tl(TCG_COND_GT, ret, sat_neg, temp, temp, sat_neg);
+
+    tcg_temp_free(sat_neg);
+}
+
+static void gen_saturate_u(TCGv ret, TCGv arg, int32_t up)
+{
+    TCGv temp = tcg_const_i32(up);
+
+    /* sat_neg = (arg > up ) ? up : arg; */
+    tcg_gen_movcond_tl(TCG_COND_GTU, ret, arg, temp, temp, arg);
+
+    tcg_temp_free(temp);
+}
+
 #define OP_COND(insn)\
 static inline void gen_cond_##insn(int cond, TCGv r1, TCGv r2, TCGv r3, \
                                    TCGv r4)                             \
@@ -332,6 +356,15 @@  static void gen_compute_branch(DisasContext *ctx, uint32_t opc,
     case OPC1_16_SBR_LOOP:
         gen_loop(ctx, r1, offset * 2 - 32);
         break;
+/* SR-format jumps */
+    case OPC1_16_SR_JI:
+        tcg_gen_andi_tl(cpu_PC, cpu_gpr_a[r1], 0xfffffffe);
+        tcg_gen_exit_tb(0);
+        break;
+    case OPC2_16_SR_RET:
+        gen_helper_ret(cpu_env);
+        tcg_gen_exit_tb(0);
+        break;
     default:
         printf("Branch Error at %x\n", ctx->pc);
     }
@@ -652,6 +685,56 @@  static void decode_sro_opc(DisasContext *ctx, int op1)
     }
 }

+static void decode_sr_system(CPUTRICOREState *env, DisasContext *ctx)
+{
+    uint32_t op2;
+    op2 = MASK_OP_SR_OP2(ctx->opcode);
+
+    switch (op2) {
+    case OPC2_16_SR_NOP:
+        break;
+    case OPC2_16_SR_RET:
+        gen_compute_branch(ctx, op2, 0, 0, 0, 0);
+        break;
+    case OPC2_16_SR_RFE:
+        gen_helper_rfe(cpu_env);
+        tcg_gen_exit_tb(0);
+        ctx->bstate = BS_BRANCH;
+        break;
+    case OPC2_16_SR_DEBUG:
+        /* raise EXCP_DEBUG */
+        break;
+    }
+}
+
+static void decode_sr_accu(CPUTRICOREState *env, DisasContext *ctx)
+{
+    uint32_t op2;
+    uint32_t r1;
+
+    r1 = MASK_OP_SR_S1D(ctx->opcode);
+    op2 = MASK_OP_SR_OP2(ctx->opcode);
+
+    switch (op2) {
+
+    case OPC2_16_SR_RSUB:
+        tcg_gen_subfi_tl(cpu_gpr_d[r1], 0, cpu_gpr_d[r1]);
+        break;
+    case OPC2_16_SR_SAT_B:
+        gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7f, -0x80);
+        break;
+    case OPC2_16_SR_SAT_BU:
+        gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xff);
+        break;
+    case OPC2_16_SR_SAT_H:
+        gen_saturate(cpu_gpr_d[r1], cpu_gpr_d[r1], 0x7fff, -0x8000);
+        break;
+    case OPC2_16_SR_SAT_HU:
+        gen_saturate_u(cpu_gpr_d[r1], cpu_gpr_d[r1], 0xffff);
+        break;
+    }
+}
+
 static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
 {
     int op1;
@@ -839,6 +922,24 @@  static void decode_16Bit_opc(CPUTRICOREState *env, DisasContext *ctx)
         const16 = MASK_OP_SSRO_OFF4(ctx->opcode);
         gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[15], const16 * 4, MO_LESL);
         break;
+/* SR-format */
+    case OPCM_16_SR_SYSTEM:
+        decode_sr_system(env, ctx);
+         break;
+    case OPCM_16_SR_ACCU:
+        decode_sr_accu(env, ctx);
+         break;
+    case OPC1_16_SR_JI:
+        r1 = MASK_OP_SR_S1D(ctx->opcode);
+        gen_compute_branch(ctx, op1, r1, 0, 0, 0);
+        break;
+    case OPC1_16_SR_NOT:
+        if (MASK_OP_SR_OP2(ctx->opcode) == 0x0) {
+            break;
+        }
+        r1 = MASK_OP_SR_S1D(ctx->opcode);
+        tcg_gen_not_tl(cpu_gpr_d[r1], cpu_gpr_d[r1]);
+        break;
     }
 }