| Message ID | 53C3ACBE.7080302@arm.com |
|---|---|
| State | New |
| Headers | show |
On Mon, Jul 14, 2014 at 11:11 AM, Jiong Wang <jiong.wang@arm.com> wrote: > currently the following testcases are disabled for arm target, > > gcc.dg/ira-shrinkwrap-prep-1.c > gcc.dg/ira-shrinkwrap-prep-2.c > gcc.dg/pr10474.c > > the reason is on arm target, register r3 is caller-saved. Normally it does > not need to be saved on entry by the prologue. However if we choose to save > it for padding then we may confuse the compiler into thinking a prologue > sequence > is required when in fact it is not. This will occur when shrink-wrapping if > r3 > is used as a scratch register and there are no other callee-saved writes. > > This situation can be avoided when other callee-saved registers are > available > and r3 is not mandatory if we choose a callee-saved register for padding. > > > Dejagnu improvements > === > -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-1.c > -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-2.c > +PASS: gcc.dg/ira-shrinkwrap-prep-1.c (test for excess errors) > +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Will split live > ranges of parameters" > +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split live-range of > register" > +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump pro_and_epilogue > "Performing shrink-wrapping" > +PASS: gcc.dg/ira-shrinkwrap-prep-2.c (test for excess errors) > +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Will split live > ranges of parameters" > +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Split live-range of > register" > +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump pro_and_epilogue > "Performing shrink-wrapping" > -UNSUPPORTED: gcc.dg/pr10474.c > +PASS: gcc.dg/pr10474.c (test for excess errors) > +PASS: gcc.dg/pr10474.c scan-rtl-dump pro_and_epilogue "Performing > shrink-wrapping" > > ok for trunk ? This is OK Ramana > > thanks. > > -- Jiong > > gcc/ > * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other > callee-saved > registers are available for padding purpose, and r3 is not mandatory, > then > prefer use those callee-saved instead of r3. > > gcc/testsuite/ > * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb > * gcc.dg/ira-shrinkwrap-prep-2.c (target): Add arm_nothumb > * gcc.dg/pr10474.c (target): Add arm_nothumb
On 22/07/14 17:29, Ramana Radhakrishnan wrote: > On Mon, Jul 14, 2014 at 11:11 AM, Jiong Wang <jiong.wang@arm.com> wrote: >> currently the following testcases are disabled for arm target, >> >> gcc.dg/ira-shrinkwrap-prep-1.c >> gcc.dg/ira-shrinkwrap-prep-2.c >> gcc.dg/pr10474.c >> >> the reason is on arm target, register r3 is caller-saved. Normally it does >> not need to be saved on entry by the prologue. However if we choose to save >> it for padding then we may confuse the compiler into thinking a prologue >> sequence >> is required when in fact it is not. This will occur when shrink-wrapping if >> r3 >> is used as a scratch register and there are no other callee-saved writes. >> >> This situation can be avoided when other callee-saved registers are >> available >> and r3 is not mandatory if we choose a callee-saved register for padding. >> >> >> Dejagnu improvements >> === >> -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-1.c >> -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-2.c >> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c (test for excess errors) >> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Will split live >> ranges of parameters" >> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split live-range of >> register" >> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump pro_and_epilogue >> "Performing shrink-wrapping" >> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c (test for excess errors) >> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Will split live >> ranges of parameters" >> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Split live-range of >> register" >> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump pro_and_epilogue >> "Performing shrink-wrapping" >> -UNSUPPORTED: gcc.dg/pr10474.c >> +PASS: gcc.dg/pr10474.c (test for excess errors) >> +PASS: gcc.dg/pr10474.c scan-rtl-dump pro_and_epilogue "Performing >> shrink-wrapping" >> >> ok for trunk ? > This is OK > > Ramana Hi all, I've committed this on Jiongs' behalf as r212927 with some minor ChangeLog modifications to make it fit into the 80 character column limit: 2014-07-23 Jiong Wang <jiong.wang@arm.com> * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other callee-saved registers are available for padding purpose and r3 is not mandatory, then prefer use those callee-saved instead of r3. 2014-07-23 Jiong Wang <jiong.wang@arm.com> * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb. * gcc.dg/ira-shrinkwrap-prep-2.c (target): Likewise. * gcc.dg/pr10474.c (target): Likewise. Kyrill >> thanks. >> >> -- Jiong >> >> gcc/ >> * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other >> callee-saved >> registers are available for padding purpose, and r3 is not mandatory, >> then >> prefer use those callee-saved instead of r3. >> >> gcc/testsuite/ >> * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb >> * gcc.dg/ira-shrinkwrap-prep-2.c (target): Add arm_nothumb >> * gcc.dg/pr10474.c (target): Add arm_nothumb
Hi all, On 23 July 2014 11:26, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote: > > On 22/07/14 17:29, Ramana Radhakrishnan wrote: >> >> On Mon, Jul 14, 2014 at 11:11 AM, Jiong Wang <jiong.wang@arm.com> wrote: >>> >>> currently the following testcases are disabled for arm target, >>> >>> gcc.dg/ira-shrinkwrap-prep-1.c >>> gcc.dg/ira-shrinkwrap-prep-2.c >>> gcc.dg/pr10474.c >>> >>> the reason is on arm target, register r3 is caller-saved. Normally it >>> does >>> not need to be saved on entry by the prologue. However if we choose to >>> save >>> it for padding then we may confuse the compiler into thinking a prologue >>> sequence >>> is required when in fact it is not. This will occur when shrink-wrapping >>> if >>> r3 >>> is used as a scratch register and there are no other callee-saved writes. >>> >>> This situation can be avoided when other callee-saved registers are >>> available >>> and r3 is not mandatory if we choose a callee-saved register for padding. >>> >>> >>> Dejagnu improvements >>> === >>> -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-1.c >>> -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-2.c >>> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c (test for excess errors) >>> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Will split live >>> ranges of parameters" >>> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split live-range >>> of >>> register" >>> +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump pro_and_epilogue >>> "Performing shrink-wrapping" >>> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c (test for excess errors) >>> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Will split live >>> ranges of parameters" >>> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Split live-range >>> of >>> register" >>> +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump pro_and_epilogue >>> "Performing shrink-wrapping" >>> -UNSUPPORTED: gcc.dg/pr10474.c >>> +PASS: gcc.dg/pr10474.c (test for excess errors) >>> +PASS: gcc.dg/pr10474.c scan-rtl-dump pro_and_epilogue "Performing >>> shrink-wrapping" >>> >>> ok for trunk ? >> >> This is OK >> >> Ramana > > > Hi all, > > I've committed this on Jiongs' behalf as r212927 with some minor ChangeLog > modifications to make it fit into the 80 character column limit: > > 2014-07-23 Jiong Wang <jiong.wang@arm.com> > > > * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other > callee-saved registers are available for padding purpose > and r3 is not mandatory, then prefer use those callee-saved > instead of r3. > > 2014-07-23 Jiong Wang <jiong.wang@arm.com> > > * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb. > * gcc.dg/ira-shrinkwrap-prep-2.c (target): Likewise. > * gcc.dg/pr10474.c (target): Likewise. > > > Kyrill > Since this commit, I've noticed a few regressions: gcc.target/arm/pr43920-2.c object-size text <= 54 gcc.target/arm/pr45701-1.c scan-assembler push\t{r3 gcc.target/arm/pr45701-1.c scan-assembler-not r8 gcc.target/arm/pr45701-2.c scan-assembler push\t{r3 gcc.target/arm/pr45701-2.c scan-assembler-not r8 (targets arm-none-linux-gnueabi, arm-none-linux-gnueabihf). Note that these tests still PASS if one forces -marm or -march=arm-v5t in the multilib flags, or if the compiler is configured --with-cpu=cortex-a57 --with-arch=armv8. Christophe. >>> thanks. >>> >>> -- Jiong >>> >>> gcc/ >>> * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other >>> callee-saved >>> registers are available for padding purpose, and r3 is not >>> mandatory, >>> then >>> prefer use those callee-saved instead of r3. >>> >>> gcc/testsuite/ >>> * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb >>> * gcc.dg/ira-shrinkwrap-prep-2.c (target): Add arm_nothumb >>> * gcc.dg/pr10474.c (target): Add arm_nothumb > > >
On 29/07/14 10:21, Christophe Lyon wrote: > Hi all, > > > On 23 July 2014 11:26, Kyrill Tkachov <kyrylo.tkachov@arm.com> wrote: >> Hi all, >> >> I've committed this on Jiongs' behalf as r212927 with some minor ChangeLog >> modifications to make it fit into the 80 character column limit: >> >> 2014-07-23 Jiong Wang <jiong.wang@arm.com> >> >> >> * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other >> callee-saved registers are available for padding purpose >> and r3 is not mandatory, then prefer use those callee-saved >> instead of r3. >> >> 2014-07-23 Jiong Wang <jiong.wang@arm.com> >> >> * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb. >> * gcc.dg/ira-shrinkwrap-prep-2.c (target): Likewise. >> * gcc.dg/pr10474.c (target): Likewise. >> >> >> Kyrill >> > Since this commit, I've noticed a few regressions: > > gcc.target/arm/pr43920-2.c object-size text <= 54 > gcc.target/arm/pr45701-1.c scan-assembler push\t{r3 > gcc.target/arm/pr45701-1.c scan-assembler-not r8 > gcc.target/arm/pr45701-2.c scan-assembler push\t{r3 > gcc.target/arm/pr45701-2.c scan-assembler-not r8 > > (targets arm-none-linux-gnueabi, arm-none-linux-gnueabihf). > > Note that these tests still PASS if one forces -marm or -march=arm-v5t > in the multilib flags, or if the compiler is configured > --with-cpu=cortex-a57 --with-arch=armv8. Hi Christophe, Indeed. I noticed these regressions also, and just posted a fix, maybe during you writing this email:) Thanks. -- Jiong > > Christophe. > > >>>> thanks. >>>> >>>> -- Jiong >>>> >>>> gcc/ >>>> * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other >>>> callee-saved >>>> registers are available for padding purpose, and r3 is not >>>> mandatory, >>>> then >>>> prefer use those callee-saved instead of r3. >>>> >>>> gcc/testsuite/ >>>> * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb >>>> * gcc.dg/ira-shrinkwrap-prep-2.c (target): Add arm_nothumb >>>> * gcc.dg/pr10474.c (target): Add arm_nothumb >> >>
diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 78cae73..d33c62c 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -20780,30 +20780,47 @@ arm_get_frame_offsets (void) { int reg = -1; + /* Register r3 is caller-saved. Normally it does not need to be + saved on entry by the prologue. However if we choose to save + it for padding then we may confuse the compiler into thinking + a prologue sequence is required when in fact it is not. This + will occur when shrink-wrapping if r3 is used as a scratch + register and there are no other callee-saved writes. + + This situation can be avoided when other callee-saved registers + are available and r3 is not mandatory if we choose a callee-saved + register for padding. */ + bool prefer_callee_reg_p = false; + /* If it is safe to use r3, then do so. This sometimes generates better code on Thumb-2 by avoiding the need to use 32-bit push/pop instructions. */ if (! any_sibcall_could_use_r3 () && arm_size_return_regs () <= 12 && (offsets->saved_regs_mask & (1 << 3)) == 0 - && (TARGET_THUMB2 + && (TARGET_THUMB2 || !(TARGET_LDRD && current_tune->prefer_ldrd_strd))) { reg = 3; + if (!(TARGET_LDRD && current_tune->prefer_ldrd_strd)) + prefer_callee_reg_p = true; + } + if (reg == -1 + || prefer_callee_reg_p) + { + for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) + { + /* Avoid fixed registers; they may be changed at + arbitrary times so it's unsafe to restore them + during the epilogue. */ + if (!fixed_regs[i] + && (offsets->saved_regs_mask & (1 << i)) == 0) + { + reg = i; + break; + } + } } - else - for (i = 4; i <= (TARGET_THUMB1 ? LAST_LO_REGNUM : 11); i++) - { - /* Avoid fixed registers; they may be changed at - arbitrary times so it's unsafe to restore them - during the epilogue. */ - if (!fixed_regs[i] - && (offsets->saved_regs_mask & (1 << i)) == 0) - { - reg = i; - break; - } - } if (reg != -1) { diff --git a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c index fc7b142..5360844 100644 --- a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c +++ b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-1.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */ +/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */ /* { dg-options "-O3 -fdump-rtl-ira -fdump-rtl-pro_and_epilogue -fno-use-caller-save" } */ long __attribute__((noinline, noclone)) diff --git a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c index 2e5a9cf..d242cac 100644 --- a/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c +++ b/gcc/testsuite/gcc.dg/ira-shrinkwrap-prep-2.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */ +/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */ /* { dg-options "-O3 -fdump-rtl-ira -fdump-rtl-pro_and_epilogue -fno-use-caller-save" } */ long __attribute__((noinline, noclone)) diff --git a/gcc/testsuite/gcc.dg/pr10474.c b/gcc/testsuite/gcc.dg/pr10474.c index 77ccc46..803fa10 100644 --- a/gcc/testsuite/gcc.dg/pr10474.c +++ b/gcc/testsuite/gcc.dg/pr10474.c @@ -1,4 +1,4 @@ -/* { dg-do compile { target { { x86_64-*-* && lp64 } || { powerpc*-*-* && lp64 } } } } */ +/* { dg-do compile { target { { x86_64-*-* && lp64 } || { { powerpc*-*-* && lp64 } || arm_nothumb } } } } */ /* { dg-options "-O3 -fdump-rtl-pro_and_epilogue" } */ void f(int *i)
currently the following testcases are disabled for arm target, gcc.dg/ira-shrinkwrap-prep-1.c gcc.dg/ira-shrinkwrap-prep-2.c gcc.dg/pr10474.c the reason is on arm target, register r3 is caller-saved. Normally it does not need to be saved on entry by the prologue. However if we choose to save it for padding then we may confuse the compiler into thinking a prologue sequence is required when in fact it is not. This will occur when shrink-wrapping if r3 is used as a scratch register and there are no other callee-saved writes. This situation can be avoided when other callee-saved registers are available and r3 is not mandatory if we choose a callee-saved register for padding. Dejagnu improvements === -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-1.c -UNSUPPORTED: gcc.dg/ira-shrinkwrap-prep-2.c +PASS: gcc.dg/ira-shrinkwrap-prep-1.c (test for excess errors) +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Will split live ranges of parameters" +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump ira "Split live-range of register" +PASS: gcc.dg/ira-shrinkwrap-prep-1.c scan-rtl-dump pro_and_epilogue "Performing shrink-wrapping" +PASS: gcc.dg/ira-shrinkwrap-prep-2.c (test for excess errors) +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Will split live ranges of parameters" +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump ira "Split live-range of register" +PASS: gcc.dg/ira-shrinkwrap-prep-2.c scan-rtl-dump pro_and_epilogue "Performing shrink-wrapping" -UNSUPPORTED: gcc.dg/pr10474.c +PASS: gcc.dg/pr10474.c (test for excess errors) +PASS: gcc.dg/pr10474.c scan-rtl-dump pro_and_epilogue "Performing shrink-wrapping" ok for trunk ? thanks. -- Jiong gcc/ * config/arm/arm.c (arm_get_frame_offsets): If both r3 and other callee-saved registers are available for padding purpose, and r3 is not mandatory, then prefer use those callee-saved instead of r3. gcc/testsuite/ * gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb * gcc.dg/ira-shrinkwrap-prep-2.c (target): Add arm_nothumb * gcc.dg/pr10474.c (target): Add arm_nothumb