@@ -72,7 +72,6 @@ u32 tegra_uart_config[3] = {
static void __init tegra_init_early(void)
{
of_register_trusted_foundations();
- tegra_init_fuse();
tegra_cpu_reset_handler_init();
tegra_powergate_init();
}
@@ -124,7 +124,7 @@ int tegra_fuse_create_sysfs(struct device *dev, int size,
return device_create_bin_file(dev, &fuse_bin_attr);
}
-void __init tegra_init_fuse(void)
+static int __init tegra_init_fuse(void)
{
struct device_node *np;
void __iomem *car_base;
@@ -138,7 +138,7 @@ void __init tegra_init_fuse(void)
iounmap(car_base);
} else {
pr_err("Could not enable fuse clk. ioremap tegra car failed.\n");
- return;
+ return -ENXIO;
}
if (tegra_get_chip_id() == TEGRA20)
@@ -152,4 +152,7 @@ void __init tegra_init_fuse(void)
tegra_sku_info.core_process_id);
pr_debug("Tegra CPU Speedo ID %d, Soc Speedo ID %d\n",
tegra_sku_info.cpu_speedo_id, tegra_sku_info.soc_speedo_id);
+
+ return 0;
}
+early_initcall(tegra_init_fuse);
@@ -37,9 +37,12 @@ u32 tegra_read_chipid(void)
u8 tegra_get_chip_id(void)
{
- u32 id = tegra_read_chipid();
+ if (!apbmisc_base) {
+ WARN(1, "Tegra Chip ID not yet available\n");
+ return 0;
+ }
- return (id >> 8) & 0xff;
+ return (tegra_read_chipid() >> 8) & 0xff;
}
u32 tegra_read_straps(void)
@@ -56,7 +56,6 @@ struct tegra_sku_info {
u32 tegra_read_straps(void);
u32 tegra_read_chipid(void);
-void tegra_init_fuse(void);
int tegra_fuse_readl(unsigned long offset, u32 *value);
extern struct tegra_sku_info tegra_sku_info;