| Message ID | 003d01cf9c13$22319460$6694bd20$@arm.com |
|---|---|
| State | New |
| Headers | show |
On 10/07/14 08:46, Terry Guo wrote: > Hi there, > > Currently the insn type of DSP-kind instructions like QSUB8 is alu_reg which > is same as other normal instructions like SUB. In order to distinguish those > DSP-kind instructions, this patch intends to replace current alu_reg with > two sub categories alu_sreg and alu_dsp_reg. Meanwhile the alus_reg is > renamed to alus_sreg in terms of consistence. This is the first patch of > this series and intends to cover the files under gcc/config/arm. Tested with > gcc regression, no new regressions. Is it ok to trunk? > > BR, > Terry > This is OK. But please wait for the review of the AArch64 code before committing (both patches need to be in one commit for consistency). R. > 2014-07-10 Terry Guo <terry.guo@arm.com> > > * config/arm/types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg. > (alus_reg): Renamed to alus_sreg. > * config/arm/arm-fixed.md: Change type of non-dsp instructions > from alu_reg to alu_sreg. Change type of dsp instructions from > alu_reg to alu_dsp_reg. > * config/arm/thumb1.md: Likewise. > * config/arm/thumb2.md: Likewise. > * config/arm/arm.c (cortexa7_older_only): Use new ALU type names. > * config/arm/arm1020e.md (1020alu_op): Replace alu_reg and alus_reg > with > alu_sreg and alus_sreg. > * config/arm/arm1026ejs.md (alu_op): Likewise. > * config/arm/arm1136jfs.md (11_alu_op): Likewise. > * config/arm/arm926ejs.md (9_alu_op): Likewise. > * config/arm/fa526.md (526_alu_op): Likewise. > * config/arm/fa606te.md (606te_alu_op): Likewise. > * config/arm/fa626te.md (626te_alu_op): Likewise. > * config/arm/fa726te.md (726te_alu_op): Likewise. > * config/arm/fmp626.md (mp626_alu_op): Likewise. > * config/arm/arm.md (core_cycles): Replace alu_reg and alus_reg with > alu_sreg, alu_dsp_reg and alus_sreg. > * config/arm/cortex-a15.md (cortex_a15_alu): Likewise. > * config/arm/cortex-a5.md (cortex_a5_alu): Likewise. > * config/arm/cortex-a53.md (cortex_a53_alu): Likewise. > * config/arm/cortex-a7.md (cortex_a7_alu_sreg): Likewise. > * config/arm/cortex-a8.md (cortex_a8_alu): Likewise. > * config/arm/cortex-a9.md (cortex_a9_dp): Likewise. > * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. > * config/arm/cortex-r4.md (cortex_r4_alu): Likewise. > * config/arm/marvell-pj4.md (pj4_alu, pj4_alu_conds): Likewise. > > > arm-new-insn-type-v3.txt > > > diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md > index 4ab9d35..5611ad1 100644 > --- a/gcc/config/arm/arm-fixed.md > +++ b/gcc/config/arm/arm-fixed.md > @@ -26,7 +26,7 @@ > "add%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "yes,no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_sreg")]) > > (define_insn "add<mode>3" > [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") > @@ -36,7 +36,7 @@ > "sadd<qaddsub_suf>%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_dsp_reg")]) > > (define_insn "usadd<mode>3" > [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") > @@ -46,7 +46,7 @@ > "uqadd<qaddsub_suf>%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_dsp_reg")]) > > (define_insn "ssadd<mode>3" > [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") > @@ -56,7 +56,7 @@ > "qadd<qaddsub_suf>%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_dsp_reg")]) > > (define_insn "sub<mode>3" > [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") > @@ -66,7 +66,7 @@ > "sub%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "yes,no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_sreg")]) > > (define_insn "sub<mode>3" > [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") > @@ -76,7 +76,7 @@ > "ssub<qaddsub_suf>%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_dsp_reg")]) > > (define_insn "ussub<mode>3" > [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") > @@ -87,7 +87,7 @@ > "uqsub<qaddsub_suf>%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_dsp_reg")]) > > (define_insn "sssub<mode>3" > [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") > @@ -97,7 +97,7 @@ > "qsub<qaddsub_suf>%?\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "predicable_short_it" "no") > - (set_attr "type" "alu_reg")]) > + (set_attr "type" "alu_dsp_reg")]) > > ;; Fractional multiplies. > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index 78cae73..942df7d 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -11710,8 +11710,9 @@ cortexa7_older_only (rtx insn) > > switch (get_attr_type (insn)) > { > - case TYPE_ALU_REG: > - case TYPE_ALUS_REG: > + case TYPE_ALU_DSP_REG: > + case TYPE_ALU_SREG: > + case TYPE_ALUS_SREG: > case TYPE_LOGIC_REG: > case TYPE_LOGICS_REG: > case TYPE_ADC_REG: > diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md > index d6ca79a..114a2fa 100644 > --- a/gcc/config/arm/arm.md > +++ b/gcc/config/arm/arm.md > @@ -320,8 +320,8 @@ > ; than one on the main cpu execution unit. > (define_attr "core_cycles" "single,multi" > (if_then_else (eq_attr "type" > - "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\ > - alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\ > + "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\ > + alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\ > alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ > logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ > logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ > @@ -602,7 +602,7 @@ > (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") > (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") > (const_string "alu_imm") > - (const_string "alu_reg"))) > + (const_string "alu_sreg"))) > ] > ) > > @@ -620,7 +620,7 @@ > sub%.\\t%0, %1, #%n2 > add%.\\t%0, %1, %2" > [(set_attr "conds" "set") > - (set_attr "type" "alus_imm,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] > ) > > (define_insn "*addsi3_compare0_scratch" > @@ -636,7 +636,7 @@ > cmn%?\\t%0, %1" > [(set_attr "conds" "set") > (set_attr "predicable" "yes") > - (set_attr "type" "alus_imm,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] > ) > > (define_insn "*compare_negsi_si" > @@ -651,7 +651,7 @@ > (set_attr "arch" "t2,*") > (set_attr "length" "2,4") > (set_attr "predicable_short_it" "yes,no") > - (set_attr "type" "alus_reg")] > + (set_attr "type" "alus_sreg")] > ) > > ;; This is the canonicalization of addsi3_compare0_for_combiner when the > @@ -669,7 +669,7 @@ > add%.\\t%0, %1, %3 > sub%.\\t%0, %1, #%n3" > [(set_attr "conds" "set") > - (set_attr "type" "alus_reg")] > + (set_attr "type" "alus_sreg")] > ) > > ;; Convert the sequence > @@ -727,7 +727,7 @@ > sub%.\\t%0, %1, #%n2 > add%.\\t%0, %1, %2" > [(set_attr "conds" "set") > - (set_attr "type" "alus_imm,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] > ) > > (define_insn "*addsi3_compare_op2" > @@ -744,7 +744,7 @@ > add%.\\t%0, %1, %2 > sub%.\\t%0, %1, #%n2" > [(set_attr "conds" "set") > - (set_attr "type" "alus_imm,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] > ) > > (define_insn "*compare_addsi2_op0" > @@ -765,7 +765,7 @@ > (set_attr "arch" "t2,t2,*,*,*") > (set_attr "predicable_short_it" "yes,yes,no,no,no") > (set_attr "length" "2,2,4,4,4") > - (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] > ) > > (define_insn "*compare_addsi2_op1" > @@ -786,7 +786,7 @@ > (set_attr "arch" "t2,t2,*,*,*") > (set_attr "predicable_short_it" "yes,yes,no,no,no") > (set_attr "length" "2,2,4,4,4") > - (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] > ) > > (define_insn "*addsi3_carryin_<optab>" > @@ -1201,7 +1201,7 @@ > (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*") > (set_attr "predicable" "yes") > (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no") > - (set_attr "type" "alu_reg,alu_reg,alu_reg,alu_reg,alu_imm,alu_imm,alu_reg,alu_reg,multiple")] > + (set_attr "type" "alu_sreg,alu_sreg,alu_sreg,alu_sreg,alu_imm,alu_imm,alu_sreg,alu_sreg,multiple")] > ) > > (define_peephole2 > @@ -1231,7 +1231,7 @@ > sub%.\\t%0, %1, %2 > rsb%.\\t%0, %2, %1" > [(set_attr "conds" "set") > - (set_attr "type" "alus_imm,alus_reg,alus_reg")] > + (set_attr "type" "alus_imm,alus_sreg,alus_sreg")] > ) > > (define_insn "subsi3_compare" > @@ -1246,7 +1246,7 @@ > sub%.\\t%0, %1, %2 > rsb%.\\t%0, %2, %1" > [(set_attr "conds" "set") > - (set_attr "type" "alus_imm,alus_reg,alus_reg")] > + (set_attr "type" "alus_imm,alus_sreg,alus_sreg")] > ) > > (define_expand "subsf3" > @@ -4366,7 +4366,7 @@ > (set_attr "predicable_short_it" "yes,no") > (set_attr "arch" "t2,*") > (set_attr "length" "4") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_expand "negsf2" > @@ -5828,7 +5828,7 @@ > return \"add\\t%0, %|pc\"; > " > [(set_attr "length" "2") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_insn "pic_add_dot_plus_eight" > @@ -5844,7 +5844,7 @@ > return \"add%?\\t%0, %|pc, %1\"; > " > [(set_attr "predicable" "yes") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_insn "tls_load_dot_plus_eight" > @@ -6857,7 +6857,7 @@ > (set_attr "length" "2,2,4,4,4") > (set_attr "predicable" "yes") > (set_attr "predicable_short_it" "yes,yes,yes,no,no") > - (set_attr "type" "alus_imm,alus_reg,alus_reg,alus_imm,alus_imm")] > + (set_attr "type" "alus_imm,alus_sreg,alus_sreg,alus_imm,alus_imm")] > ) > > (define_insn "*cmpsi_shiftsi" > @@ -9430,10 +9430,10 @@ > (set_attr_alternative "type" > [(if_then_else (match_operand 3 "const_int_operand" "") > (const_string "alu_imm" ) > - (const_string "alu_reg")) > + (const_string "alu_sreg")) > (const_string "alu_imm") > - (const_string "alu_reg") > - (const_string "alu_reg")])] > + (const_string "alu_sreg") > + (const_string "alu_sreg")])] > ) > > (define_insn "*ifcompare_move_plus" > @@ -9470,7 +9470,7 @@ > sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" > [(set_attr "conds" "use") > (set_attr "length" "4,4,8,8") > - (set_attr "type" "alu_reg,alu_imm,multiple,multiple")] > + (set_attr "type" "alu_sreg,alu_imm,multiple,multiple")] > ) > > (define_insn "*ifcompare_arith_arith" > diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md > index 0206ea2..c157730 100644 > --- a/gcc/config/arm/arm1020e.md > +++ b/gcc/config/arm/arm1020e.md > @@ -67,7 +67,7 @@ > (define_insn_reservation "1020alu_op" 1 > (and (eq_attr "tune" "arm1020e,arm1022e") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,\ > diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md > index 3f290b4..f8c66e9 100644 > --- a/gcc/config/arm/arm1026ejs.md > +++ b/gcc/config/arm/arm1026ejs.md > @@ -67,7 +67,7 @@ > (define_insn_reservation "alu_op" 1 > (and (eq_attr "tune" "arm1026ejs") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,\ > diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md > index 9e941da..a3c61a8 100644 > --- a/gcc/config/arm/arm1136jfs.md > +++ b/gcc/config/arm/arm1136jfs.md > @@ -76,7 +76,7 @@ > (define_insn_reservation "11_alu_op" 2 > (and (eq_attr "tune" "arm1136js,arm1136jfs") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,\ > diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md > index 883935d..c6e154a 100644 > --- a/gcc/config/arm/arm926ejs.md > +++ b/gcc/config/arm/arm926ejs.md > @@ -59,7 +59,7 @@ > (define_insn_reservation "9_alu_op" 1 > (and (eq_attr "tune" "arm926ejs") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > alu_shift_imm,alus_shift_imm,\ > diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md > index b3f126a..9477d82 100644 > --- a/gcc/config/arm/cortex-a15.md > +++ b/gcc/config/arm/cortex-a15.md > @@ -62,9 +62,9 @@ > (define_insn_reservation "cortex_a15_alu" 2 > (and (eq_attr "tune" "cortexa15") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,rev,\ > + adr,bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg,\ > mov_imm,mov_reg,\ > mvn_imm,mvn_reg,\ > diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md > index eed098e..0cf8ad9 100644 > --- a/gcc/config/arm/cortex-a5.md > +++ b/gcc/config/arm/cortex-a5.md > @@ -59,9 +59,9 @@ > (define_insn_reservation "cortex_a5_alu" 2 > (and (eq_attr "tune" "cortexa5") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,rev,\ > + adr,bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg,\ > mov_imm,mov_reg,mvn_imm,mvn_reg,\ > mrs,multiple,no_insn")) > diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md > index a629bd6..b000a94 100644 > --- a/gcc/config/arm/cortex-a53.md > +++ b/gcc/config/arm/cortex-a53.md > @@ -73,9 +73,9 @@ > (define_insn_reservation "cortex_a53_alu" 2 > (and (eq_attr "tune" "cortexa53") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,csel,rev,\ > + adr,bfm,csel,rev,alu_dsp_reg,\ > shift_imm,shift_reg,\ > mov_imm,mov_reg,mvn_imm,mvn_reg,\ > mrs,multiple,no_insn")) > diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md > index 8291d7f..ed0b1e2 100644 > --- a/gcc/config/arm/cortex-a7.md > +++ b/gcc/config/arm/cortex-a7.md > @@ -133,11 +133,11 @@ > > ;; ALU instruction with register operands can dual-issue > ;; with a younger immediate-based instruction. > -(define_insn_reservation "cortex_a7_alu_reg" 2 > +(define_insn_reservation "cortex_a7_alu_sreg" 2 > (and (eq_attr "tune" "cortexa7") > - (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\ > + (eq_attr "type" "alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - bfm,rev,\ > + bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg,mov_reg,mvn_reg")) > "cortex_a7_ex1") > > @@ -153,14 +153,14 @@ > "cortex_a7_ex1") > > ;; Forwarding path for unshifted operands. > -(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" > - "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul") > +(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift" > + "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_mul") > > -(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" > +(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift" > "cortex_a7_store*" > "arm_no_early_store_addr_dep") > > -(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" > +(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift" > "cortex_a7_alu_shift" > "arm_no_early_alu_shift_dep") > > diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md > index b272472..8ef6c99 100644 > --- a/gcc/config/arm/cortex-a8.md > +++ b/gcc/config/arm/cortex-a8.md > @@ -86,9 +86,9 @@ > (define_insn_reservation "cortex_a8_alu" 2 > (and (eq_attr "tune" "cortexa8") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,clz,rbit,rev,\ > + adr,bfm,clz,rbit,rev,alu_dsp_reg,\ > shift_imm,shift_reg,\ > multiple,no_insn")) > "cortex_a8_default") > diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md > index a888896..feac547 100644 > --- a/gcc/config/arm/cortex-a9.md > +++ b/gcc/config/arm/cortex-a9.md > @@ -81,9 +81,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") > (define_insn_reservation "cortex_a9_dp" 2 > (and (eq_attr "tune" "cortexa9") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,rev,\ > + adr,bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg,\ > mov_imm,mov_reg,mvn_imm,mvn_reg,\ > mov_shift_reg,mov_shift,\ > diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md > index 690ce75..fb9997a 100644 > --- a/gcc/config/arm/cortex-m4.md > +++ b/gcc/config/arm/cortex-m4.md > @@ -32,9 +32,9 @@ > (define_insn_reservation "cortex_m4_alu" 1 > (and (eq_attr "tune" "cortexm4") > (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,rev,\ > + adr,bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg,extend,\ > alu_shift_imm,alus_shift_imm,\ > logic_shift_imm,logics_shift_imm,\ > diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md > index f000124..9dc906a 100644 > --- a/gcc/config/arm/cortex-r4.md > +++ b/gcc/config/arm/cortex-r4.md > @@ -79,7 +79,7 @@ > (define_insn_reservation "cortex_r4_alu" 2 > (and (eq_attr "tune_cortexr4" "yes") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,mvn_imm,mvn_reg")) > diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md > index c345fdf..fc58d34 100644 > --- a/gcc/config/arm/fa526.md > +++ b/gcc/config/arm/fa526.md > @@ -63,7 +63,7 @@ > (define_insn_reservation "526_alu_op" 1 > (and (eq_attr "tune" "fa526") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,\ > diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md > index 01ecfc8..432461d 100644 > --- a/gcc/config/arm/fa606te.md > +++ b/gcc/config/arm/fa606te.md > @@ -63,7 +63,7 @@ > (define_insn_reservation "606te_alu_op" 1 > (and (eq_attr "tune" "fa606te") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,extend,\ > diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md > index e615bae..e5ba9b4 100644 > --- a/gcc/config/arm/fa626te.md > +++ b/gcc/config/arm/fa626te.md > @@ -69,7 +69,7 @@ > (define_insn_reservation "626te_alu_op" 1 > (and (eq_attr "tune" "fa626,fa626te") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,\ > diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md > index 225b2cf..5af6736 100644 > --- a/gcc/config/arm/fa726te.md > +++ b/gcc/config/arm/fa726te.md > @@ -87,7 +87,7 @@ > (define_insn_reservation "726te_alu_op" 1 > (and (eq_attr "tune" "fa726te") > (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ > - alu_reg,alus_reg,logic_reg,logics_reg,\ > + alu_sreg,alus_sreg,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > shift_imm,shift_reg,\ > diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md > index 439054d..24e9b6a 100644 > --- a/gcc/config/arm/fmp626.md > +++ b/gcc/config/arm/fmp626.md > @@ -63,7 +63,7 @@ > ;; ALU operations > (define_insn_reservation "mp626_alu_op" 1 > (and (eq_attr "tune" "fmp626") > - (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ > + (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\ > logic_imm,logics_imm,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > adr,bfm,rev,\ > diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md > index 0b9d6eb..85f5f05 100644 > --- a/gcc/config/arm/marvell-pj4.md > +++ b/gcc/config/arm/marvell-pj4.md > @@ -53,20 +53,20 @@ > > (define_insn_reservation "pj4_alu" 1 > (and (eq_attr "tune" "marvell_pj4") > - (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ > + (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\ > logic_imm,logics_imm,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,rev,\ > + adr,bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg") > (not (eq_attr "conds" "set"))) > "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") > > (define_insn_reservation "pj4_alu_conds" 4 > (and (eq_attr "tune" "marvell_pj4") > - (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ > + (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\ > logic_imm,logics_imm,logic_reg,logics_reg,\ > adc_imm,adcs_imm,adc_reg,adcs_reg,\ > - adr,bfm,rev,\ > + adr,bfm,rev,alu_dsp_reg,\ > shift_imm,shift_reg") > (eq_attr "conds" "set")) > "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") > diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md > index c044fd5..cd1adf4 100644 > --- a/gcc/config/arm/thumb1.md > +++ b/gcc/config/arm/thumb1.md > @@ -81,8 +81,8 @@ > operands[2] = GEN_INT (INTVAL (operands[2]) - offset); > } > [(set_attr "length" "2,2,2,2,2,2,2,4,4,4") > - (set_attr "type" "alus_imm,alus_imm,alus_reg,alus_reg,alus_reg, > - alus_reg,alus_reg,multiple,multiple,multiple")] > + (set_attr "type" "alus_imm,alus_imm,alus_sreg,alus_sreg,alus_sreg, > + alus_sreg,alus_sreg,multiple,multiple,multiple")] > ) > > ;; Reloading and elimination of the frame pointer can > @@ -118,7 +118,7 @@ > "sub\\t%0, %1, %2" > [(set_attr "length" "2") > (set_attr "conds" "set") > - (set_attr "type" "alus_reg")] > + (set_attr "type" "alus_sreg")] > ) > > ; Unfortunately with the Thumb the '&'/'0' trick can fails when operands > diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md > index 6ea0810..029a679 100644 > --- a/gcc/config/arm/thumb2.md > +++ b/gcc/config/arm/thumb2.md > @@ -1117,7 +1117,7 @@ > "%I3%!\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "length" "2") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_insn "*thumb2_shiftsi3_short" > @@ -1171,7 +1171,7 @@ > " > [(set_attr "predicable" "yes") > (set_attr "length" "2") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_insn "*thumb2_subsi_short" > @@ -1183,7 +1183,7 @@ > "sub%!\\t%0, %1, %2" > [(set_attr "predicable" "yes") > (set_attr "length" "2") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_peephole2 > @@ -1236,7 +1236,7 @@ > " > [(set_attr "conds" "set") > (set_attr "length" "2,2,4") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > (define_insn "*thumb2_addsi3_compare0_scratch" > @@ -1261,7 +1261,7 @@ > " > [(set_attr "conds" "set") > (set_attr "length" "2,2,4,4") > - (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_reg")] > + (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_sreg")] > ) > > (define_insn "*thumb2_mulsi_short" > @@ -1367,7 +1367,7 @@ > "neg%!\t%0, %1" > [(set_attr "predicable" "yes") > (set_attr "length" "2") > - (set_attr "type" "alu_reg")] > + (set_attr "type" "alu_sreg")] > ) > > ; Constants for op 2 will never be given to these patterns. > diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md > index efbf7a7..ff74aaa 100644 > --- a/gcc/config/arm/types.md > +++ b/gcc/config/arm/types.md > @@ -35,17 +35,19 @@ > ; alu_imm any arithmetic instruction that doesn't have a shifted > ; operand and has an immediate operand. This > ; excludes MOV, MVN and RSB(S) immediate. > -; alu_reg any arithmetic instruction that doesn't have a shifted > +; alu_sreg any arithmetic instruction that doesn't have a shifted > ; or an immediate operand. This excludes > -; MOV and MVN but includes MOVT. This is also the default. > +; MOV and MVN but includes MOVT. This also excludes > +; DSP-kind instructions. This is also the default. > ; alu_shift_imm any arithmetic instruction that has a source operand > ; shifted by a constant. This excludes simple shifts. > ; alu_shift_reg as alu_shift_imm, with the shift amount specified in a > ; register. > +; alu_dsp_reg any DSP-kind instruction like QSUB8. > ; alus_ext From ARMv8-A: as alu_ext, setting condition flags. > ; AArch64 Only. > ; alus_imm as alu_imm, setting condition flags. > -; alus_reg as alu_reg, setting condition flags. > +; alus_sreg as alu_sreg, setting condition flags. > ; alus_shift_imm as alu_shift_imm, setting condition flags. > ; alus_shift_reg as alu_shift_reg, setting condition flags. > ; bfm bitfield move operation. > @@ -540,12 +542,13 @@ > adr,\ > alu_ext,\ > alu_imm,\ > - alu_reg,\ > + alu_sreg,\ > alu_shift_imm,\ > alu_shift_reg,\ > + alu_dsp_reg,\ > alus_ext,\ > alus_imm,\ > - alus_reg,\ > + alus_sreg,\ > alus_shift_imm,\ > alus_shift_reg,\ > bfm,\ >
diff --git a/gcc/config/arm/arm-fixed.md b/gcc/config/arm/arm-fixed.md index 4ab9d35..5611ad1 100644 --- a/gcc/config/arm/arm-fixed.md +++ b/gcc/config/arm/arm-fixed.md @@ -26,7 +26,7 @@ "add%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_sreg")]) (define_insn "add<mode>3" [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") @@ -36,7 +36,7 @@ "sadd<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_dsp_reg")]) (define_insn "usadd<mode>3" [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") @@ -46,7 +46,7 @@ "uqadd<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_dsp_reg")]) (define_insn "ssadd<mode>3" [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") @@ -56,7 +56,7 @@ "qadd<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_dsp_reg")]) (define_insn "sub<mode>3" [(set (match_operand:FIXED 0 "s_register_operand" "=l,r") @@ -66,7 +66,7 @@ "sub%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_sreg")]) (define_insn "sub<mode>3" [(set (match_operand:ADDSUB 0 "s_register_operand" "=r") @@ -76,7 +76,7 @@ "ssub<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_dsp_reg")]) (define_insn "ussub<mode>3" [(set (match_operand:UQADDSUB 0 "s_register_operand" "=r") @@ -87,7 +87,7 @@ "uqsub<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_dsp_reg")]) (define_insn "sssub<mode>3" [(set (match_operand:QADDSUB 0 "s_register_operand" "=r") @@ -97,7 +97,7 @@ "qsub<qaddsub_suf>%?\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "predicable_short_it" "no") - (set_attr "type" "alu_reg")]) + (set_attr "type" "alu_dsp_reg")]) ;; Fractional multiplies. diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 78cae73..942df7d 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -11710,8 +11710,9 @@ cortexa7_older_only (rtx insn) switch (get_attr_type (insn)) { - case TYPE_ALU_REG: - case TYPE_ALUS_REG: + case TYPE_ALU_DSP_REG: + case TYPE_ALU_SREG: + case TYPE_ALUS_SREG: case TYPE_LOGIC_REG: case TYPE_LOGICS_REG: case TYPE_ADC_REG: diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index d6ca79a..114a2fa 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -320,8 +320,8 @@ ; than one on the main cpu execution unit. (define_attr "core_cycles" "single,multi" (if_then_else (eq_attr "type" - "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_reg,\ - alu_shift_imm, alu_shift_reg, alus_ext, alus_imm, alus_reg,\ + "adc_imm, adc_reg, adcs_imm, adcs_reg, adr, alu_ext, alu_imm, alu_sreg,\ + alu_shift_imm, alu_shift_reg, alu_dsp_reg, alus_ext, alus_imm, alus_sreg,\ alus_shift_imm, alus_shift_reg, bfm, csel, rev, logic_imm, logic_reg,\ logic_shift_imm, logic_shift_reg, logics_imm, logics_reg,\ logics_shift_imm, logics_shift_reg, extend, shift_imm, float, fcsel,\ @@ -602,7 +602,7 @@ (set_attr "arch" "t2,t2,t2,t2,*,*,*,t2,t2,*,*,a,t2,t2,*") (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") (const_string "alu_imm") - (const_string "alu_reg"))) + (const_string "alu_sreg"))) ] ) @@ -620,7 +620,7 @@ sub%.\\t%0, %1, #%n2 add%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) (define_insn "*addsi3_compare0_scratch" @@ -636,7 +636,7 @@ cmn%?\\t%0, %1" [(set_attr "conds" "set") (set_attr "predicable" "yes") - (set_attr "type" "alus_imm,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) (define_insn "*compare_negsi_si" @@ -651,7 +651,7 @@ (set_attr "arch" "t2,*") (set_attr "length" "2,4") (set_attr "predicable_short_it" "yes,no") - (set_attr "type" "alus_reg")] + (set_attr "type" "alus_sreg")] ) ;; This is the canonicalization of addsi3_compare0_for_combiner when the @@ -669,7 +669,7 @@ add%.\\t%0, %1, %3 sub%.\\t%0, %1, #%n3" [(set_attr "conds" "set") - (set_attr "type" "alus_reg")] + (set_attr "type" "alus_sreg")] ) ;; Convert the sequence @@ -727,7 +727,7 @@ sub%.\\t%0, %1, #%n2 add%.\\t%0, %1, %2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) (define_insn "*addsi3_compare_op2" @@ -744,7 +744,7 @@ add%.\\t%0, %1, %2 sub%.\\t%0, %1, #%n2" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_imm,alus_sreg")] ) (define_insn "*compare_addsi2_op0" @@ -765,7 +765,7 @@ (set_attr "arch" "t2,t2,*,*,*") (set_attr "predicable_short_it" "yes,yes,no,no,no") (set_attr "length" "2,2,4,4,4") - (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] ) (define_insn "*compare_addsi2_op1" @@ -786,7 +786,7 @@ (set_attr "arch" "t2,t2,*,*,*") (set_attr "predicable_short_it" "yes,yes,no,no,no") (set_attr "length" "2,2,4,4,4") - (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_imm,alus_sreg")] ) (define_insn "*addsi3_carryin_<optab>" @@ -1201,7 +1201,7 @@ (set_attr "arch" "t2,t2,t2,t2,*,*,*,*,*") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,yes,yes,yes,no,no,no,no,no") - (set_attr "type" "alu_reg,alu_reg,alu_reg,alu_reg,alu_imm,alu_imm,alu_reg,alu_reg,multiple")] + (set_attr "type" "alu_sreg,alu_sreg,alu_sreg,alu_sreg,alu_imm,alu_imm,alu_sreg,alu_sreg,multiple")] ) (define_peephole2 @@ -1231,7 +1231,7 @@ sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_reg,alus_reg")] + (set_attr "type" "alus_imm,alus_sreg,alus_sreg")] ) (define_insn "subsi3_compare" @@ -1246,7 +1246,7 @@ sub%.\\t%0, %1, %2 rsb%.\\t%0, %2, %1" [(set_attr "conds" "set") - (set_attr "type" "alus_imm,alus_reg,alus_reg")] + (set_attr "type" "alus_imm,alus_sreg,alus_sreg")] ) (define_expand "subsf3" @@ -4366,7 +4366,7 @@ (set_attr "predicable_short_it" "yes,no") (set_attr "arch" "t2,*") (set_attr "length" "4") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_expand "negsf2" @@ -5828,7 +5828,7 @@ return \"add\\t%0, %|pc\"; " [(set_attr "length" "2") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_insn "pic_add_dot_plus_eight" @@ -5844,7 +5844,7 @@ return \"add%?\\t%0, %|pc, %1\"; " [(set_attr "predicable" "yes") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_insn "tls_load_dot_plus_eight" @@ -6857,7 +6857,7 @@ (set_attr "length" "2,2,4,4,4") (set_attr "predicable" "yes") (set_attr "predicable_short_it" "yes,yes,yes,no,no") - (set_attr "type" "alus_imm,alus_reg,alus_reg,alus_imm,alus_imm")] + (set_attr "type" "alus_imm,alus_sreg,alus_sreg,alus_imm,alus_imm")] ) (define_insn "*cmpsi_shiftsi" @@ -9430,10 +9430,10 @@ (set_attr_alternative "type" [(if_then_else (match_operand 3 "const_int_operand" "") (const_string "alu_imm" ) - (const_string "alu_reg")) + (const_string "alu_sreg")) (const_string "alu_imm") - (const_string "alu_reg") - (const_string "alu_reg")])] + (const_string "alu_sreg") + (const_string "alu_sreg")])] ) (define_insn "*ifcompare_move_plus" @@ -9470,7 +9470,7 @@ sub%D4\\t%0, %2, #%n3\;mov%d4\\t%0, %1" [(set_attr "conds" "use") (set_attr "length" "4,4,8,8") - (set_attr "type" "alu_reg,alu_imm,multiple,multiple")] + (set_attr "type" "alu_sreg,alu_imm,multiple,multiple")] ) (define_insn "*ifcompare_arith_arith" diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md index 0206ea2..c157730 100644 --- a/gcc/config/arm/arm1020e.md +++ b/gcc/config/arm/arm1020e.md @@ -67,7 +67,7 @@ (define_insn_reservation "1020alu_op" 1 (and (eq_attr "tune" "arm1020e,arm1022e") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ diff --git a/gcc/config/arm/arm1026ejs.md b/gcc/config/arm/arm1026ejs.md index 3f290b4..f8c66e9 100644 --- a/gcc/config/arm/arm1026ejs.md +++ b/gcc/config/arm/arm1026ejs.md @@ -67,7 +67,7 @@ (define_insn_reservation "alu_op" 1 (and (eq_attr "tune" "arm1026ejs") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ diff --git a/gcc/config/arm/arm1136jfs.md b/gcc/config/arm/arm1136jfs.md index 9e941da..a3c61a8 100644 --- a/gcc/config/arm/arm1136jfs.md +++ b/gcc/config/arm/arm1136jfs.md @@ -76,7 +76,7 @@ (define_insn_reservation "11_alu_op" 2 (and (eq_attr "tune" "arm1136js,arm1136jfs") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ diff --git a/gcc/config/arm/arm926ejs.md b/gcc/config/arm/arm926ejs.md index 883935d..c6e154a 100644 --- a/gcc/config/arm/arm926ejs.md +++ b/gcc/config/arm/arm926ejs.md @@ -59,7 +59,7 @@ (define_insn_reservation "9_alu_op" 1 (and (eq_attr "tune" "arm926ejs") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ alu_shift_imm,alus_shift_imm,\ diff --git a/gcc/config/arm/cortex-a15.md b/gcc/config/arm/cortex-a15.md index b3f126a..9477d82 100644 --- a/gcc/config/arm/cortex-a15.md +++ b/gcc/config/arm/cortex-a15.md @@ -62,9 +62,9 @@ (define_insn_reservation "cortex_a15_alu" 2 (and (eq_attr "tune" "cortexa15") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,rev,\ + adr,bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg,\ mov_imm,mov_reg,\ mvn_imm,mvn_reg,\ diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md index eed098e..0cf8ad9 100644 --- a/gcc/config/arm/cortex-a5.md +++ b/gcc/config/arm/cortex-a5.md @@ -59,9 +59,9 @@ (define_insn_reservation "cortex_a5_alu" 2 (and (eq_attr "tune" "cortexa5") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,rev,\ + adr,bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mrs,multiple,no_insn")) diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md index a629bd6..b000a94 100644 --- a/gcc/config/arm/cortex-a53.md +++ b/gcc/config/arm/cortex-a53.md @@ -73,9 +73,9 @@ (define_insn_reservation "cortex_a53_alu" 2 (and (eq_attr "tune" "cortexa53") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,csel,rev,\ + adr,bfm,csel,rev,alu_dsp_reg,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mrs,multiple,no_insn")) diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md index 8291d7f..ed0b1e2 100644 --- a/gcc/config/arm/cortex-a7.md +++ b/gcc/config/arm/cortex-a7.md @@ -133,11 +133,11 @@ ;; ALU instruction with register operands can dual-issue ;; with a younger immediate-based instruction. -(define_insn_reservation "cortex_a7_alu_reg" 2 +(define_insn_reservation "cortex_a7_alu_sreg" 2 (and (eq_attr "tune" "cortexa7") - (eq_attr "type" "alu_reg,alus_reg,logic_reg,logics_reg,\ + (eq_attr "type" "alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - bfm,rev,\ + bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg,mov_reg,mvn_reg")) "cortex_a7_ex1") @@ -153,14 +153,14 @@ "cortex_a7_ex1") ;; Forwarding path for unshifted operands. -(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" - "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_mul") +(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift" + "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_mul") -(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" +(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift" "cortex_a7_store*" "arm_no_early_store_addr_dep") -(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_reg,cortex_a7_alu_shift" +(define_bypass 1 "cortex_a7_alu_imm,cortex_a7_alu_sreg,cortex_a7_alu_shift" "cortex_a7_alu_shift" "arm_no_early_alu_shift_dep") diff --git a/gcc/config/arm/cortex-a8.md b/gcc/config/arm/cortex-a8.md index b272472..8ef6c99 100644 --- a/gcc/config/arm/cortex-a8.md +++ b/gcc/config/arm/cortex-a8.md @@ -86,9 +86,9 @@ (define_insn_reservation "cortex_a8_alu" 2 (and (eq_attr "tune" "cortexa8") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,clz,rbit,rev,\ + adr,bfm,clz,rbit,rev,alu_dsp_reg,\ shift_imm,shift_reg,\ multiple,no_insn")) "cortex_a8_default") diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md index a888896..feac547 100644 --- a/gcc/config/arm/cortex-a9.md +++ b/gcc/config/arm/cortex-a9.md @@ -81,9 +81,9 @@ cortex_a9_p1_e2 + cortex_a9_p0_e1 + cortex_a9_p1_e1") (define_insn_reservation "cortex_a9_dp" 2 (and (eq_attr "tune" "cortexa9") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,rev,\ + adr,bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg,\ mov_imm,mov_reg,mvn_imm,mvn_reg,\ mov_shift_reg,mov_shift,\ diff --git a/gcc/config/arm/cortex-m4.md b/gcc/config/arm/cortex-m4.md index 690ce75..fb9997a 100644 --- a/gcc/config/arm/cortex-m4.md +++ b/gcc/config/arm/cortex-m4.md @@ -32,9 +32,9 @@ (define_insn_reservation "cortex_m4_alu" 1 (and (eq_attr "tune" "cortexm4") (ior (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,rev,\ + adr,bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg,extend,\ alu_shift_imm,alus_shift_imm,\ logic_shift_imm,logics_shift_imm,\ diff --git a/gcc/config/arm/cortex-r4.md b/gcc/config/arm/cortex-r4.md index f000124..9dc906a 100644 --- a/gcc/config/arm/cortex-r4.md +++ b/gcc/config/arm/cortex-r4.md @@ -79,7 +79,7 @@ (define_insn_reservation "cortex_r4_alu" 2 (and (eq_attr "tune_cortexr4" "yes") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,mvn_imm,mvn_reg")) diff --git a/gcc/config/arm/fa526.md b/gcc/config/arm/fa526.md index c345fdf..fc58d34 100644 --- a/gcc/config/arm/fa526.md +++ b/gcc/config/arm/fa526.md @@ -63,7 +63,7 @@ (define_insn_reservation "526_alu_op" 1 (and (eq_attr "tune" "fa526") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ diff --git a/gcc/config/arm/fa606te.md b/gcc/config/arm/fa606te.md index 01ecfc8..432461d 100644 --- a/gcc/config/arm/fa606te.md +++ b/gcc/config/arm/fa606te.md @@ -63,7 +63,7 @@ (define_insn_reservation "606te_alu_op" 1 (and (eq_attr "tune" "fa606te") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,extend,\ diff --git a/gcc/config/arm/fa626te.md b/gcc/config/arm/fa626te.md index e615bae..e5ba9b4 100644 --- a/gcc/config/arm/fa626te.md +++ b/gcc/config/arm/fa626te.md @@ -69,7 +69,7 @@ (define_insn_reservation "626te_alu_op" 1 (and (eq_attr "tune" "fa626,fa626te") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ diff --git a/gcc/config/arm/fa726te.md b/gcc/config/arm/fa726te.md index 225b2cf..5af6736 100644 --- a/gcc/config/arm/fa726te.md +++ b/gcc/config/arm/fa726te.md @@ -87,7 +87,7 @@ (define_insn_reservation "726te_alu_op" 1 (and (eq_attr "tune" "fa726te") (eq_attr "type" "alu_imm,alus_imm,logic_imm,logics_imm,\ - alu_reg,alus_reg,logic_reg,logics_reg,\ + alu_sreg,alus_sreg,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ shift_imm,shift_reg,\ diff --git a/gcc/config/arm/fmp626.md b/gcc/config/arm/fmp626.md index 439054d..24e9b6a 100644 --- a/gcc/config/arm/fmp626.md +++ b/gcc/config/arm/fmp626.md @@ -63,7 +63,7 @@ ;; ALU operations (define_insn_reservation "mp626_alu_op" 1 (and (eq_attr "tune" "fmp626") - (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ + (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\ logic_imm,logics_imm,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ adr,bfm,rev,\ diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md index 0b9d6eb..85f5f05 100644 --- a/gcc/config/arm/marvell-pj4.md +++ b/gcc/config/arm/marvell-pj4.md @@ -53,20 +53,20 @@ (define_insn_reservation "pj4_alu" 1 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ + (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\ logic_imm,logics_imm,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,rev,\ + adr,bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg") (not (eq_attr "conds" "set"))) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") (define_insn_reservation "pj4_alu_conds" 4 (and (eq_attr "tune" "marvell_pj4") - (eq_attr "type" "alu_imm,alus_imm,alu_reg,alus_reg,\ + (eq_attr "type" "alu_imm,alus_imm,alu_sreg,alus_sreg,\ logic_imm,logics_imm,logic_reg,logics_reg,\ adc_imm,adcs_imm,adc_reg,adcs_reg,\ - adr,bfm,rev,\ + adr,bfm,rev,alu_dsp_reg,\ shift_imm,shift_reg") (eq_attr "conds" "set")) "pj4_is,(pj4_alu1,pj4_w1+pj4_cp)|(pj4_alu2,pj4_w2+pj4_cp)") diff --git a/gcc/config/arm/thumb1.md b/gcc/config/arm/thumb1.md index c044fd5..cd1adf4 100644 --- a/gcc/config/arm/thumb1.md +++ b/gcc/config/arm/thumb1.md @@ -81,8 +81,8 @@ operands[2] = GEN_INT (INTVAL (operands[2]) - offset); } [(set_attr "length" "2,2,2,2,2,2,2,4,4,4") - (set_attr "type" "alus_imm,alus_imm,alus_reg,alus_reg,alus_reg, - alus_reg,alus_reg,multiple,multiple,multiple")] + (set_attr "type" "alus_imm,alus_imm,alus_sreg,alus_sreg,alus_sreg, + alus_sreg,alus_sreg,multiple,multiple,multiple")] ) ;; Reloading and elimination of the frame pointer can @@ -118,7 +118,7 @@ "sub\\t%0, %1, %2" [(set_attr "length" "2") (set_attr "conds" "set") - (set_attr "type" "alus_reg")] + (set_attr "type" "alus_sreg")] ) ; Unfortunately with the Thumb the '&'/'0' trick can fails when operands diff --git a/gcc/config/arm/thumb2.md b/gcc/config/arm/thumb2.md index 6ea0810..029a679 100644 --- a/gcc/config/arm/thumb2.md +++ b/gcc/config/arm/thumb2.md @@ -1117,7 +1117,7 @@ "%I3%!\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "length" "2") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_insn "*thumb2_shiftsi3_short" @@ -1171,7 +1171,7 @@ " [(set_attr "predicable" "yes") (set_attr "length" "2") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_insn "*thumb2_subsi_short" @@ -1183,7 +1183,7 @@ "sub%!\\t%0, %1, %2" [(set_attr "predicable" "yes") (set_attr "length" "2") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_peephole2 @@ -1236,7 +1236,7 @@ " [(set_attr "conds" "set") (set_attr "length" "2,2,4") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) (define_insn "*thumb2_addsi3_compare0_scratch" @@ -1261,7 +1261,7 @@ " [(set_attr "conds" "set") (set_attr "length" "2,2,4,4") - (set_attr "type" "alus_imm,alus_reg,alus_imm,alus_reg")] + (set_attr "type" "alus_imm,alus_sreg,alus_imm,alus_sreg")] ) (define_insn "*thumb2_mulsi_short" @@ -1367,7 +1367,7 @@ "neg%!\t%0, %1" [(set_attr "predicable" "yes") (set_attr "length" "2") - (set_attr "type" "alu_reg")] + (set_attr "type" "alu_sreg")] ) ; Constants for op 2 will never be given to these patterns. diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md index efbf7a7..ff74aaa 100644 --- a/gcc/config/arm/types.md +++ b/gcc/config/arm/types.md @@ -35,17 +35,19 @@ ; alu_imm any arithmetic instruction that doesn't have a shifted ; operand and has an immediate operand. This ; excludes MOV, MVN and RSB(S) immediate. -; alu_reg any arithmetic instruction that doesn't have a shifted +; alu_sreg any arithmetic instruction that doesn't have a shifted ; or an immediate operand. This excludes -; MOV and MVN but includes MOVT. This is also the default. +; MOV and MVN but includes MOVT. This also excludes +; DSP-kind instructions. This is also the default. ; alu_shift_imm any arithmetic instruction that has a source operand ; shifted by a constant. This excludes simple shifts. ; alu_shift_reg as alu_shift_imm, with the shift amount specified in a ; register. +; alu_dsp_reg any DSP-kind instruction like QSUB8. ; alus_ext From ARMv8-A: as alu_ext, setting condition flags. ; AArch64 Only. ; alus_imm as alu_imm, setting condition flags. -; alus_reg as alu_reg, setting condition flags. +; alus_sreg as alu_sreg, setting condition flags. ; alus_shift_imm as alu_shift_imm, setting condition flags. ; alus_shift_reg as alu_shift_reg, setting condition flags. ; bfm bitfield move operation. @@ -540,12 +542,13 @@ adr,\ alu_ext,\ alu_imm,\ - alu_reg,\ + alu_sreg,\ alu_shift_imm,\ alu_shift_reg,\ + alu_dsp_reg,\ alus_ext,\ alus_imm,\ - alus_reg,\ + alus_sreg,\ alus_shift_imm,\ alus_shift_reg,\ bfm,\
Hi there, Currently the insn type of DSP-kind instructions like QSUB8 is alu_reg which is same as other normal instructions like SUB. In order to distinguish those DSP-kind instructions, this patch intends to replace current alu_reg with two sub categories alu_sreg and alu_dsp_reg. Meanwhile the alus_reg is renamed to alus_sreg in terms of consistence. This is the first patch of this series and intends to cover the files under gcc/config/arm. Tested with gcc regression, no new regressions. Is it ok to trunk? BR, Terry 2014-07-10 Terry Guo <terry.guo@arm.com> * config/arm/types.md (alu_reg): Replaced by alu_sreg and alu_dsp_reg. (alus_reg): Renamed to alus_sreg. * config/arm/arm-fixed.md: Change type of non-dsp instructions from alu_reg to alu_sreg. Change type of dsp instructions from alu_reg to alu_dsp_reg. * config/arm/thumb1.md: Likewise. * config/arm/thumb2.md: Likewise. * config/arm/arm.c (cortexa7_older_only): Use new ALU type names. * config/arm/arm1020e.md (1020alu_op): Replace alu_reg and alus_reg with alu_sreg and alus_sreg. * config/arm/arm1026ejs.md (alu_op): Likewise. * config/arm/arm1136jfs.md (11_alu_op): Likewise. * config/arm/arm926ejs.md (9_alu_op): Likewise. * config/arm/fa526.md (526_alu_op): Likewise. * config/arm/fa606te.md (606te_alu_op): Likewise. * config/arm/fa626te.md (626te_alu_op): Likewise. * config/arm/fa726te.md (726te_alu_op): Likewise. * config/arm/fmp626.md (mp626_alu_op): Likewise. * config/arm/arm.md (core_cycles): Replace alu_reg and alus_reg with alu_sreg, alu_dsp_reg and alus_sreg. * config/arm/cortex-a15.md (cortex_a15_alu): Likewise. * config/arm/cortex-a5.md (cortex_a5_alu): Likewise. * config/arm/cortex-a53.md (cortex_a53_alu): Likewise. * config/arm/cortex-a7.md (cortex_a7_alu_sreg): Likewise. * config/arm/cortex-a8.md (cortex_a8_alu): Likewise. * config/arm/cortex-a9.md (cortex_a9_dp): Likewise. * config/arm/cortex-m4.md (cortex_m4_alu): Likewise. * config/arm/cortex-r4.md (cortex_r4_alu): Likewise. * config/arm/marvell-pj4.md (pj4_alu, pj4_alu_conds): Likewise.